Reset strategy (sync vs async) in Verilog - Hands-On Comparison

Reset Strategy: Synchronous vs Asynchronous in Verilog

📖 Scenario: You are designing a simple digital counter circuit in Verilog. The counter needs a reset signal to start counting from zero. There are two common ways to handle reset signals: synchronous reset and asynchronous reset.Understanding the difference helps you design reliable circuits that behave correctly when reset is triggered.

🎯 Goal: Build two versions of a 4-bit counter in Verilog: one with a synchronous reset and one with an asynchronous reset. Learn how to write each reset style and see how they differ in code.

📋 What You'll Learn

Create a 4-bit register called count.

Use a clock signal called clk.

Use a reset signal called rst.

Implement a synchronous reset counter that resets count to 0 on the rising edge of clk when rst is high.

Implement an asynchronous reset counter that resets count to 0 immediately when rst is high, regardless of clk.

💡 Why This Matters

🌍 Real World

Reset signals are essential in digital circuits to start devices in a known state. Choosing the right reset strategy affects circuit reliability and timing.

💼 Career

Hardware engineers and FPGA developers must understand reset strategies to design robust digital systems that work correctly in real hardware.

1

Create the basic 4-bit counter with clock and reset signals

Write a Verilog module named sync_reset_counter with inputs clk and rst, and a 4-bit output register count. Initialize count to 0.

Verilog

module sync_reset_counter(input clk, input rst, output reg [3:0] count);
// Your code here
endmodule

Hint

Start by declaring the module and its ports. Use initial to set count to zero.

2

Add synchronous reset logic to the counter

Inside the sync_reset_counter module, add an always block triggered on the rising edge of clk. Inside it, write an if statement that checks if rst is high. If yes, set count to 0; otherwise, increment count by 1.

Verilog

module sync_reset_counter(input clk, input rst, output reg [3:0] count);
    initial count = 4'b0000;
    // Add synchronous reset logic here
endmodule

Hint

Use always @(posedge clk) to trigger on clock. Inside, check if (rst) to reset count. Use else to increment.

3

Create an asynchronous reset counter module

Write a new Verilog module named async_reset_counter with inputs clk and rst, and a 4-bit output register count. Add an always block triggered on the rising edge of clk or the rising edge of rst. Inside, if rst is high, set count to 0 immediately; otherwise, increment count by 1 on clock.

Verilog

module sync_reset_counter(input clk, input rst, output reg [3:0] count);
    initial count = 4'b0000;
    always @(posedge clk) begin
        if (rst) begin
            count <= 4'b0000;
        end else begin
            count <= count + 1;
        end
    end
endmodule

// Your code here for async_reset_counter

Hint

Use always @(posedge clk or posedge rst) to detect reset immediately. Reset count when rst is high, else increment on clock.

4

Display the difference in reset behavior

Write two initial blocks to simulate the counters. For each counter, print the value of count after applying reset and clock pulses. Use $display to show the counter values for both synchronous and asynchronous reset counters.

Verilog

module sync_reset_counter(input clk, input rst, output reg [3:0] count);
    initial count = 4'b0000;
    always @(posedge clk) begin
        if (rst) begin
            count <= 4'b0000;
        end else begin
            count <= count + 1;
        end
    end
endmodule

module async_reset_counter(input clk, input rst, output reg [3:0] count);
    initial count = 4'b0000;
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            count <= 4'b0000;
        end else begin
            count <= count + 1;
        end
    end
endmodule

// Your code here to simulate and display counts

Hint

Use a testbench module with clock toggling every 5 units. Apply reset high for 10 units, then low. Use $display to print time and counts.

Practice

1. What is the main difference between a synchronous reset and an asynchronous reset in Verilog?

easy

A. Synchronous reset is triggered by the clock edge, asynchronous reset works immediately.

B. Synchronous reset works immediately, asynchronous reset waits for the clock edge.

C. Both resets work only on the clock's rising edge.

D. Asynchronous reset requires a clock, synchronous reset does not.

Solution

1. Step 1: Understand synchronous reset behavior

   Synchronous reset activates only on the clock edge, so the reset signal is sampled with the clock.

2. Step 2: Understand asynchronous reset behavior

   Asynchronous reset activates immediately when asserted, independent of the clock.

3. Final Answer:

   Synchronous reset is triggered by the clock edge, asynchronous reset works immediately. -> Option A

4. Quick Check:

   Reset timing difference = synchronous on clock, async immediate [OK]

Hint: Sync reset waits clock, async reset acts immediately [OK]

Common Mistakes:

• Confusing which reset depends on clock
• Thinking async reset waits for clock edge
• Assuming both resets behave the same

2. Which of the following is the correct Verilog syntax for a synchronous reset inside an always block?

easy

A. always @(posedge clk or posedge rst) begin if (rst) q <= 0; else q <= d; end

B. always @(posedge clk) begin if (rst) q <= 0; else q <= d; end

C. always @(rst) begin if (rst) q <= 0; else q <= d; end

D. always @(negedge rst) begin q <= 0; end

Solution

1. Step 1: Identify synchronous reset syntax

   Synchronous reset is checked inside a clock-only sensitivity list, typically @(posedge clk).

2. Step 2: Check reset condition inside the block

   The reset condition is inside the always block, using if (rst) to reset synchronously.

3. Final Answer:

   always @(posedge clk) begin if (rst) q <= 0; else q <= d; end -> Option B

4. Quick Check:

   Sync reset inside clock-only always block [OK]

Hint: Sync reset inside clock-only always block [OK]

Common Mistakes:

• Including reset in sensitivity list for sync reset
• Using asynchronous sensitivity list for sync reset
• Missing clock edge in always block

3. Given the following Verilog code, what will be the value of q after the asynchronous reset rst is deasserted?

reg q;
always @(posedge clk or posedge rst) begin
  if (rst) q <= 1'b0;
  else q <= d;
end

medium

A. q will immediately reset to 0 when rst is asserted, then follow d on clock edges.

B. q will reset to 0 only on the next clock edge after rst is asserted.

C. q will never reset because rst is asynchronous.

D. q will hold its previous value regardless of rst.

Solution

1. Step 1: Analyze asynchronous reset sensitivity

   The always block triggers on posedge clk or posedge rst, so when rst is asserted, q resets immediately.

2. Step 2: Behavior after reset deassertion

   After rst is deasserted, q updates on clock edges following the value of d.

3. Final Answer:

   q will immediately reset to 0 when rst is asserted, then follow d on clock edges. -> Option A

4. Quick Check:

   Async reset immediate, then sync update [OK]

Hint: Async reset triggers immediately, sync updates after [OK]

Common Mistakes:

• Thinking async reset waits for clock edge
• Assuming q holds value during reset
• Confusing reset assertion and deassertion timing

4. Identify the error in this Verilog code snippet implementing a synchronous reset:

always @(posedge clk or posedge rst) begin
  if (rst) q <= 0;
  else q <= d;
end

medium

A. The assignment operator should be = instead of <=.

B. The reset condition should be checked outside the always block.

C. The clock edge should be negedge instead of posedge.

D. The reset should not be in the sensitivity list for synchronous reset.

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset should only be sensitive to the clock edge, not the reset signal.

2. Step 2: Identify the error

   Including posedge rst makes the reset asynchronous, which contradicts the synchronous reset intent.

3. Final Answer:

   The reset should not be in the sensitivity list for synchronous reset. -> Option D

4. Quick Check:

   Sync reset sensitivity = clock only [OK]

Hint: Sync reset sensitivity list excludes reset signal [OK]

Common Mistakes:

• Including reset in sensitivity list for sync reset
• Misunderstanding sensitivity list purpose
• Using blocking assignment instead of non-blocking

5. You need to design a flip-flop with a reset that must clear the output immediately when asserted, but also synchronize with the clock to avoid metastability issues. Which reset strategy is best and how should it be implemented?

hard

A. Use an asynchronous reset without synchronization.

B. Use a synchronous reset only, ignoring immediate reset requirement.

C. Use an asynchronous reset with a synchronizer circuit on the reset signal.

D. Use two separate resets: one async and one sync, both controlling the flip-flop.

Solution

1. Step 1: Understand immediate reset need

   Immediate clearing requires asynchronous reset to react without waiting for clock.

2. Step 2: Avoid metastability by synchronizing reset

   To prevent metastability, the asynchronous reset signal should be passed through synchronizer flip-flops before use.

3. Step 3: Combine both requirements

   Using async reset with synchronizer achieves immediate reset and safe clock domain crossing.

4. Final Answer:

   Use an asynchronous reset with a synchronizer circuit on the reset signal. -> Option C

5. Quick Check:

   Async reset + synchronizer = immediate and safe reset [OK]

Hint: Async reset plus synchronizer avoids metastability [OK]

Common Mistakes:

• Using only synchronous reset ignoring immediate reset
• Using async reset without synchronization causing metastability
• Trying to use two resets on same flip-flop incorrectly