Reset strategy (sync vs async) in Verilog - Quick Revision & Key Differences

Recall & Review

beginner

What is a synchronous reset in Verilog?

A synchronous reset is a reset signal that is checked and applied only on the active clock edge, ensuring the reset happens in sync with the clock.

beginner

What is an asynchronous reset in Verilog?

An asynchronous reset immediately resets the circuit regardless of the clock, reacting instantly when the reset signal is asserted.

intermediate

Why might you choose a synchronous reset over an asynchronous reset?

Synchronous resets avoid issues like metastability and glitches because the reset is aligned with the clock, making timing analysis easier.

intermediate

What is a common problem with asynchronous resets?

Asynchronous resets can cause metastability or glitches if the reset is released near the clock edge, leading to unpredictable circuit behavior.

beginner

How do you typically implement a synchronous reset in Verilog?

Inside an always block triggered by the clock, check if the reset signal is active; if yes, reset registers, else proceed with normal operation.

Which reset type reacts immediately without waiting for the clock?

A Asynchronous reset

B Synchronous reset

C Both reset types

D Neither reset type

Asynchronous resets act immediately when asserted, independent of the clock.

What is a benefit of synchronous resets?

A Immediate reset without clock delay

B Simpler timing analysis

C No need for clock signal

D Avoids reset glitches completely

Synchronous resets align with the clock, making timing analysis simpler.

What risk is higher with asynchronous resets?

A Metastability

B Slower reset

C Clock skew

D No reset

Asynchronous resets can cause metastability if released near clock edges.

In Verilog, where do you check the reset signal for a synchronous reset?

A In a combinational always block

B Outside any always block

C Only in initial blocks

D Inside the clocked always block

Synchronous resets are checked inside the always block triggered by the clock.

Which reset type is generally preferred for FPGA designs to avoid glitches?

A No reset

B Asynchronous reset

C Synchronous reset

D Both are equally preferred

Synchronous resets are preferred in FPGA designs to reduce glitches.

Explain the difference between synchronous and asynchronous resets in Verilog.

Think about when the reset signal affects the circuit relative to the clock.

Describe one advantage and one disadvantage of using asynchronous resets.

Consider speed versus reliability.

Practice

1. What is the main difference between a synchronous reset and an asynchronous reset in Verilog?

easy

A. Synchronous reset is triggered by the clock edge, asynchronous reset works immediately.

B. Synchronous reset works immediately, asynchronous reset waits for the clock edge.

C. Both resets work only on the clock's rising edge.

D. Asynchronous reset requires a clock, synchronous reset does not.

Solution

1. Step 1: Understand synchronous reset behavior

   Synchronous reset activates only on the clock edge, so the reset signal is sampled with the clock.

2. Step 2: Understand asynchronous reset behavior

   Asynchronous reset activates immediately when asserted, independent of the clock.

3. Final Answer:

   Synchronous reset is triggered by the clock edge, asynchronous reset works immediately. -> Option A

4. Quick Check:

   Reset timing difference = synchronous on clock, async immediate [OK]

Hint: Sync reset waits clock, async reset acts immediately [OK]

Common Mistakes:

• Confusing which reset depends on clock
• Thinking async reset waits for clock edge
• Assuming both resets behave the same

2. Which of the following is the correct Verilog syntax for a synchronous reset inside an always block?

easy

A. always @(posedge clk or posedge rst) begin if (rst) q <= 0; else q <= d; end

B. always @(posedge clk) begin if (rst) q <= 0; else q <= d; end

C. always @(rst) begin if (rst) q <= 0; else q <= d; end

D. always @(negedge rst) begin q <= 0; end

Solution

1. Step 1: Identify synchronous reset syntax

   Synchronous reset is checked inside a clock-only sensitivity list, typically @(posedge clk).

2. Step 2: Check reset condition inside the block

   The reset condition is inside the always block, using if (rst) to reset synchronously.

3. Final Answer:

   always @(posedge clk) begin if (rst) q <= 0; else q <= d; end -> Option B

4. Quick Check:

   Sync reset inside clock-only always block [OK]

Hint: Sync reset inside clock-only always block [OK]

Common Mistakes:

• Including reset in sensitivity list for sync reset
• Using asynchronous sensitivity list for sync reset
• Missing clock edge in always block

3. Given the following Verilog code, what will be the value of q after the asynchronous reset rst is deasserted?

reg q;
always @(posedge clk or posedge rst) begin
  if (rst) q <= 1'b0;
  else q <= d;
end

medium

A. q will immediately reset to 0 when rst is asserted, then follow d on clock edges.

B. q will reset to 0 only on the next clock edge after rst is asserted.

C. q will never reset because rst is asynchronous.

D. q will hold its previous value regardless of rst.

Solution

1. Step 1: Analyze asynchronous reset sensitivity

   The always block triggers on posedge clk or posedge rst, so when rst is asserted, q resets immediately.

2. Step 2: Behavior after reset deassertion

   After rst is deasserted, q updates on clock edges following the value of d.

3. Final Answer:

   q will immediately reset to 0 when rst is asserted, then follow d on clock edges. -> Option A

4. Quick Check:

   Async reset immediate, then sync update [OK]

Hint: Async reset triggers immediately, sync updates after [OK]

Common Mistakes:

• Thinking async reset waits for clock edge
• Assuming q holds value during reset
• Confusing reset assertion and deassertion timing

4. Identify the error in this Verilog code snippet implementing a synchronous reset:

always @(posedge clk or posedge rst) begin
  if (rst) q <= 0;
  else q <= d;
end

medium

A. The assignment operator should be = instead of <=.

B. The reset condition should be checked outside the always block.

C. The clock edge should be negedge instead of posedge.

D. The reset should not be in the sensitivity list for synchronous reset.

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset should only be sensitive to the clock edge, not the reset signal.

2. Step 2: Identify the error

   Including posedge rst makes the reset asynchronous, which contradicts the synchronous reset intent.

3. Final Answer:

   The reset should not be in the sensitivity list for synchronous reset. -> Option D

4. Quick Check:

   Sync reset sensitivity = clock only [OK]

Hint: Sync reset sensitivity list excludes reset signal [OK]

Common Mistakes:

• Including reset in sensitivity list for sync reset
• Misunderstanding sensitivity list purpose
• Using blocking assignment instead of non-blocking

5. You need to design a flip-flop with a reset that must clear the output immediately when asserted, but also synchronize with the clock to avoid metastability issues. Which reset strategy is best and how should it be implemented?

hard

A. Use an asynchronous reset without synchronization.

B. Use a synchronous reset only, ignoring immediate reset requirement.

C. Use an asynchronous reset with a synchronizer circuit on the reset signal.

D. Use two separate resets: one async and one sync, both controlling the flip-flop.

Solution

1. Step 1: Understand immediate reset need

   Immediate clearing requires asynchronous reset to react without waiting for clock.

2. Step 2: Avoid metastability by synchronizing reset

   To prevent metastability, the asynchronous reset signal should be passed through synchronizer flip-flops before use.

3. Step 3: Combine both requirements

   Using async reset with synchronizer achieves immediate reset and safe clock domain crossing.

4. Final Answer:

   Use an asynchronous reset with a synchronizer circuit on the reset signal. -> Option C

5. Quick Check:

   Async reset + synchronizer = immediate and safe reset [OK]

Hint: Async reset plus synchronizer avoids metastability [OK]

Common Mistakes:

• Using only synchronous reset ignoring immediate reset
• Using async reset without synchronization causing metastability
• Trying to use two resets on same flip-flop incorrectly