Reset strategy (sync vs async) in Verilog - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of synchronous reset flip-flop

What is the output q after the following Verilog code runs for one clock cycle with reset = 1 and d = 1?

Verilog

module sync_reset_ff(input clk, input reset, input d, output reg q);
  always @(posedge clk) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

A q = d (unknown)

B q = 1

C q = 0

D q retains previous value

💡 Hint

Think about when the reset affects the output in a synchronous reset.

In a synchronous reset, the reset signal is checked only on the clock's rising edge. If reset is high at that time, q is set to 0 regardless of d.

❓ Predict Output

intermediate

Output of asynchronous reset flip-flop

What is the output q immediately after reset goes high, regardless of the clock?

Verilog

module async_reset_ff(input clk, input reset, input d, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

A q = 0 immediately

B q changes only on next clock edge

C q = d immediately

D q retains previous value

💡 Hint

Asynchronous reset affects output immediately when reset changes.

Because reset is in the sensitivity list with posedge, q is set to 0 immediately when reset goes high, without waiting for clock.

🧠 Conceptual

advanced

Difference in reset timing behavior

Which statement best describes the difference between synchronous and asynchronous reset in flip-flops?

A Synchronous reset affects output immediately; asynchronous reset affects output only on clock edge.

B Synchronous reset affects output only on clock edge; asynchronous reset affects output immediately when reset changes.

C Both resets affect output only on clock edge but differ in polarity.

D Both resets affect output immediately but differ in signal duration.

💡 Hint

Think about when the reset signal is checked in each case.

Synchronous reset is sampled on clock edges, so output changes only then. Asynchronous reset triggers output change immediately on reset signal change.

🔧 Debug

advanced

Identify error in asynchronous reset code

Which option contains a syntax or logic error in implementing asynchronous reset?

Verilog

always @(posedge clk or posedge reset) begin
  if (reset == 1'b1)
    q <= 1'b0;
  else
    q <= d;
end

A always @(posedge clk) begin if (reset) q <= 0; else q <= d; end

B always @(posedge clk or posedge reset) begin if (reset) q <= 0; else q <= d; end

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D always @(posedge clk or posedge reset) begin if (reset == 1'b0) q <= 0; else q <= d; end

💡 Hint

Check the condition that triggers reset.

Option D resets q when reset is 0, which is incorrect for active-high reset. The reset condition should be when reset is 1.

🚀 Application

expert

Choosing reset strategy for FPGA design

You are designing a synchronous digital system on an FPGA that requires a reliable reset. Which reset strategy is generally preferred and why?

A Synchronous reset, because it avoids metastability and timing issues related to asynchronous signals.

B Asynchronous reset, because it guarantees immediate reset regardless of clock.

C Asynchronous reset, because it uses fewer resources in FPGA.

D Synchronous reset, because it allows reset to be triggered at any time asynchronously.

💡 Hint

Consider FPGA internal timing and metastability risks.

Synchronous resets are preferred in FPGA designs because asynchronous resets can cause metastability and timing problems. Synchronous resets are controlled by the clock, making timing predictable.

Practice

1. What is the main difference between a synchronous reset and an asynchronous reset in Verilog?

easy

A. Synchronous reset is triggered by the clock edge, asynchronous reset works immediately.

B. Synchronous reset works immediately, asynchronous reset waits for the clock edge.

C. Both resets work only on the clock's rising edge.

D. Asynchronous reset requires a clock, synchronous reset does not.

Solution

1. Step 1: Understand synchronous reset behavior

   Synchronous reset activates only on the clock edge, so the reset signal is sampled with the clock.

2. Step 2: Understand asynchronous reset behavior

   Asynchronous reset activates immediately when asserted, independent of the clock.

3. Final Answer:

   Synchronous reset is triggered by the clock edge, asynchronous reset works immediately. -> Option A

4. Quick Check:

   Reset timing difference = synchronous on clock, async immediate [OK]

Hint: Sync reset waits clock, async reset acts immediately [OK]

Common Mistakes:

• Confusing which reset depends on clock
• Thinking async reset waits for clock edge
• Assuming both resets behave the same

2. Which of the following is the correct Verilog syntax for a synchronous reset inside an always block?

easy

A. always @(posedge clk or posedge rst) begin if (rst) q <= 0; else q <= d; end

B. always @(posedge clk) begin if (rst) q <= 0; else q <= d; end

C. always @(rst) begin if (rst) q <= 0; else q <= d; end

D. always @(negedge rst) begin q <= 0; end

Solution

1. Step 1: Identify synchronous reset syntax

   Synchronous reset is checked inside a clock-only sensitivity list, typically @(posedge clk).

2. Step 2: Check reset condition inside the block

   The reset condition is inside the always block, using if (rst) to reset synchronously.

3. Final Answer:

   always @(posedge clk) begin if (rst) q <= 0; else q <= d; end -> Option B

4. Quick Check:

   Sync reset inside clock-only always block [OK]

Hint: Sync reset inside clock-only always block [OK]

Common Mistakes:

• Including reset in sensitivity list for sync reset
• Using asynchronous sensitivity list for sync reset
• Missing clock edge in always block

3. Given the following Verilog code, what will be the value of q after the asynchronous reset rst is deasserted?

reg q;
always @(posedge clk or posedge rst) begin
  if (rst) q <= 1'b0;
  else q <= d;
end

medium

A. q will immediately reset to 0 when rst is asserted, then follow d on clock edges.

B. q will reset to 0 only on the next clock edge after rst is asserted.

C. q will never reset because rst is asynchronous.

D. q will hold its previous value regardless of rst.

Solution

1. Step 1: Analyze asynchronous reset sensitivity

   The always block triggers on posedge clk or posedge rst, so when rst is asserted, q resets immediately.

2. Step 2: Behavior after reset deassertion

   After rst is deasserted, q updates on clock edges following the value of d.

3. Final Answer:

   q will immediately reset to 0 when rst is asserted, then follow d on clock edges. -> Option A

4. Quick Check:

   Async reset immediate, then sync update [OK]

Hint: Async reset triggers immediately, sync updates after [OK]

Common Mistakes:

• Thinking async reset waits for clock edge
• Assuming q holds value during reset
• Confusing reset assertion and deassertion timing

4. Identify the error in this Verilog code snippet implementing a synchronous reset:

always @(posedge clk or posedge rst) begin
  if (rst) q <= 0;
  else q <= d;
end

medium

A. The assignment operator should be = instead of <=.

B. The reset condition should be checked outside the always block.

C. The clock edge should be negedge instead of posedge.

D. The reset should not be in the sensitivity list for synchronous reset.

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset should only be sensitive to the clock edge, not the reset signal.

2. Step 2: Identify the error

   Including posedge rst makes the reset asynchronous, which contradicts the synchronous reset intent.

3. Final Answer:

   The reset should not be in the sensitivity list for synchronous reset. -> Option D

4. Quick Check:

   Sync reset sensitivity = clock only [OK]

Hint: Sync reset sensitivity list excludes reset signal [OK]

Common Mistakes:

• Including reset in sensitivity list for sync reset
• Misunderstanding sensitivity list purpose
• Using blocking assignment instead of non-blocking

5. You need to design a flip-flop with a reset that must clear the output immediately when asserted, but also synchronize with the clock to avoid metastability issues. Which reset strategy is best and how should it be implemented?

hard

A. Use an asynchronous reset without synchronization.

B. Use a synchronous reset only, ignoring immediate reset requirement.

C. Use an asynchronous reset with a synchronizer circuit on the reset signal.

D. Use two separate resets: one async and one sync, both controlling the flip-flop.

Solution

1. Step 1: Understand immediate reset need

   Immediate clearing requires asynchronous reset to react without waiting for clock.

2. Step 2: Avoid metastability by synchronizing reset

   To prevent metastability, the asynchronous reset signal should be passed through synchronizer flip-flops before use.

3. Step 3: Combine both requirements

   Using async reset with synchronizer achieves immediate reset and safe clock domain crossing.

4. Final Answer:

   Use an asynchronous reset with a synchronizer circuit on the reset signal. -> Option C

5. Quick Check:

   Async reset + synchronizer = immediate and safe reset [OK]

Hint: Async reset plus synchronizer avoids metastability [OK]

Common Mistakes:

• Using only synchronous reset ignoring immediate reset
• Using async reset without synchronization causing metastability
• Trying to use two resets on same flip-flop incorrectly