Reset strategy (sync vs async) in Verilog - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a synchronous reset signal in a flip-flop.

Verilog

always @(posedge clk) begin
  if ([1]) reset_reg <= 1'b1;
  else reset_reg <= 1'b0;
end

Drag options to blanks, or click blank then click option'

Areset_async

Breset_sync

Creset

Drst_n

Attempts:

3 left

💡 Hint

Common Mistakes

Using asynchronous reset signal inside a synchronous block.

The synchronous reset is checked inside the clocked always block using the reset signal.

2fill in blank

medium

Complete the code to declare an asynchronous reset in a flip-flop sensitivity list.

Verilog

always @(posedge clk or posedge [1]) begin
  if (reset) q <= 1'b0;
  else q <= d;
end

Drag options to blanks, or click blank then click option'

Areset_async

Breset_sync

Cclk

Drst_n

Attempts:

3 left

💡 Hint

Common Mistakes

Forgetting to add reset to sensitivity list for async reset.

Asynchronous reset is included in the sensitivity list with the reset signal.

3fill in blank

hard

Fix the error in the asynchronous reset block sensitivity list.

Verilog

always @(posedge clk or [1] reset) begin
  if (reset) q <= 1'b0;
  else q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge

Blevel

Cedge

Dnegedge

Attempts:

3 left

💡 Hint

Common Mistakes

Omitting 'posedge' or 'negedge' before reset signal.

The sensitivity list requires 'posedge' or 'negedge' before the reset signal.

4fill in blank

hard

Fill both blanks to implement a synchronous reset with active low signal.

Verilog

always @(posedge clk) begin
  if ([1] == [2]) q <= 1'b0;
  else q <= d;
end

Drag options to blanks, or click blank then click option'

Areset_n

B1'b0

C1'b1

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Checking active low reset against 1 instead of 0.

Active low reset means reset_n equals 0 to reset the flip-flop synchronously.

5fill in blank

hard

Fill all three blanks to implement an asynchronous active low reset flip-flop.

Verilog

always @(posedge clk or [1] [2]) begin
  if ([3] == 1'b0) q <= 1'b0;
  else q <= d;
end

Drag options to blanks, or click blank then click option'

Anegedge

Breset_n

Creset

Dposedge

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge instead of negedge for active low reset.

Asynchronous active low reset uses negedge of reset_n in sensitivity list and checks if reset_n is 0.

Practice

1. What is the main difference between a synchronous reset and an asynchronous reset in Verilog?

easy

A. Synchronous reset is triggered by the clock edge, asynchronous reset works immediately.

B. Synchronous reset works immediately, asynchronous reset waits for the clock edge.

C. Both resets work only on the clock's rising edge.

D. Asynchronous reset requires a clock, synchronous reset does not.

Solution

1. Step 1: Understand synchronous reset behavior

   Synchronous reset activates only on the clock edge, so the reset signal is sampled with the clock.

2. Step 2: Understand asynchronous reset behavior

   Asynchronous reset activates immediately when asserted, independent of the clock.

3. Final Answer:

   Synchronous reset is triggered by the clock edge, asynchronous reset works immediately. -> Option A

4. Quick Check:

   Reset timing difference = synchronous on clock, async immediate [OK]

Hint: Sync reset waits clock, async reset acts immediately [OK]

Common Mistakes:

• Confusing which reset depends on clock
• Thinking async reset waits for clock edge
• Assuming both resets behave the same

2. Which of the following is the correct Verilog syntax for a synchronous reset inside an always block?

easy

A. always @(posedge clk or posedge rst) begin if (rst) q <= 0; else q <= d; end

B. always @(posedge clk) begin if (rst) q <= 0; else q <= d; end

C. always @(rst) begin if (rst) q <= 0; else q <= d; end

D. always @(negedge rst) begin q <= 0; end

Solution

1. Step 1: Identify synchronous reset syntax

   Synchronous reset is checked inside a clock-only sensitivity list, typically @(posedge clk).

2. Step 2: Check reset condition inside the block

   The reset condition is inside the always block, using if (rst) to reset synchronously.

3. Final Answer:

   always @(posedge clk) begin if (rst) q <= 0; else q <= d; end -> Option B

4. Quick Check:

   Sync reset inside clock-only always block [OK]

Hint: Sync reset inside clock-only always block [OK]

Common Mistakes:

• Including reset in sensitivity list for sync reset
• Using asynchronous sensitivity list for sync reset
• Missing clock edge in always block

3. Given the following Verilog code, what will be the value of q after the asynchronous reset rst is deasserted?

reg q;
always @(posedge clk or posedge rst) begin
  if (rst) q <= 1'b0;
  else q <= d;
end

medium

A. q will immediately reset to 0 when rst is asserted, then follow d on clock edges.

B. q will reset to 0 only on the next clock edge after rst is asserted.

C. q will never reset because rst is asynchronous.

D. q will hold its previous value regardless of rst.

Solution

1. Step 1: Analyze asynchronous reset sensitivity

   The always block triggers on posedge clk or posedge rst, so when rst is asserted, q resets immediately.

2. Step 2: Behavior after reset deassertion

   After rst is deasserted, q updates on clock edges following the value of d.

3. Final Answer:

   q will immediately reset to 0 when rst is asserted, then follow d on clock edges. -> Option A

4. Quick Check:

   Async reset immediate, then sync update [OK]

Hint: Async reset triggers immediately, sync updates after [OK]

Common Mistakes:

• Thinking async reset waits for clock edge
• Assuming q holds value during reset
• Confusing reset assertion and deassertion timing

4. Identify the error in this Verilog code snippet implementing a synchronous reset:

always @(posedge clk or posedge rst) begin
  if (rst) q <= 0;
  else q <= d;
end

medium

A. The assignment operator should be = instead of <=.

B. The reset condition should be checked outside the always block.

C. The clock edge should be negedge instead of posedge.

D. The reset should not be in the sensitivity list for synchronous reset.

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset should only be sensitive to the clock edge, not the reset signal.

2. Step 2: Identify the error

   Including posedge rst makes the reset asynchronous, which contradicts the synchronous reset intent.

3. Final Answer:

   The reset should not be in the sensitivity list for synchronous reset. -> Option D

4. Quick Check:

   Sync reset sensitivity = clock only [OK]

Hint: Sync reset sensitivity list excludes reset signal [OK]

Common Mistakes:

• Including reset in sensitivity list for sync reset
• Misunderstanding sensitivity list purpose
• Using blocking assignment instead of non-blocking

5. You need to design a flip-flop with a reset that must clear the output immediately when asserted, but also synchronize with the clock to avoid metastability issues. Which reset strategy is best and how should it be implemented?

hard

A. Use an asynchronous reset without synchronization.

B. Use a synchronous reset only, ignoring immediate reset requirement.

C. Use an asynchronous reset with a synchronizer circuit on the reset signal.

D. Use two separate resets: one async and one sync, both controlling the flip-flop.

Solution

1. Step 1: Understand immediate reset need

   Immediate clearing requires asynchronous reset to react without waiting for clock.

2. Step 2: Avoid metastability by synchronizing reset

   To prevent metastability, the asynchronous reset signal should be passed through synchronizer flip-flops before use.

3. Step 3: Combine both requirements

   Using async reset with synchronizer achieves immediate reset and safe clock domain crossing.

4. Final Answer:

   Use an asynchronous reset with a synchronizer circuit on the reset signal. -> Option C

5. Quick Check:

   Async reset + synchronizer = immediate and safe reset [OK]

Hint: Async reset plus synchronizer avoids metastability [OK]

Common Mistakes:

• Using only synchronous reset ignoring immediate reset
• Using async reset without synchronization causing metastability
• Trying to use two resets on same flip-flop incorrectly