Randomized test stimulus in Verilog - Step-by-Step Execution

Concept Flow - Randomized test stimulus

Start Testbench

↓

Initialize Signals

↓

Generate Random Inputs

↓

Apply Inputs to DUT

↓

Wait for Response

↓

Check Output

↓

Repeat or Finish

The testbench starts, initializes signals, generates random inputs, applies them to the device under test (DUT), waits for the response, checks output, and repeats or finishes.

Execution Sample

Verilog

initial begin
  repeat (5) begin
    a = $random;
    b = $random;
    #10;
  end
end

This code generates random values for signals 'a' and 'b' five times, waiting 10 time units between each.

Execution Table

Iteration	a (random)	b (random)	Delay (#10)	Action
1	a= -123456789	b= 987654321	Wait 10 time units	Apply random inputs
2	a= 234567890	b= -876543210	Wait 10 time units	Apply random inputs
3	a= -345678901	b= 765432109	Wait 10 time units	Apply random inputs
4	a= 456789012	b= -654321098	Wait 10 time units	Apply random inputs
5	a= -567890123	b= 543210987	Wait 10 time units	Apply random inputs
Exit	No more iterations	No more iterations	Test complete	Stop

💡 After 5 iterations, the repeat loop ends and the test stimulus stops.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	Final
a	undefined	-123456789	234567890	-345678901	456789012	-567890123	last random value
b	undefined	987654321	-876543210	765432109	-654321098	543210987	last random value

Key Moments - 3 Insights

Why do the values of 'a' and 'b' change every iteration?

Because the $random function generates a new random number each time inside the repeat loop, as shown in the execution_table rows 1 to 5.

What does the '#10;' statement do in the loop?

It causes the simulation to wait 10 time units before the next iteration, allowing the DUT to process inputs, as seen in the 'Delay (#10)' column.

Why does the loop stop after 5 iterations?

Because the repeat(5) limits the loop to exactly 5 cycles, after which the test stimulus ends, as indicated in the exit_note.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of 'a' at iteration 3?

A -345678901

B 234567890

C 456789012

D -123456789

💡 Hint

Check the 'a (random)' column at row for iteration 3 in the execution_table.

At which iteration does the delay of 10 time units occur?

A Only after iteration 5

B Before iteration 1

C After every iteration from 1 to 5

D No delay occurs

💡 Hint

Look at the 'Delay (#10)' column in the execution_table for each iteration.

If the repeat count changed to 3, how many rows would the execution_table have before exit?

A 3

B 4

C 5

D 6

💡 Hint

The table has one row per iteration plus one exit row; see current 5 iterations plus exit row.

Concept Snapshot

Randomized test stimulus in Verilog:
- Use $random to generate random values.
- Apply inside a repeat loop for multiple tests.
- Use #delay to wait between inputs.
- Helps test DUT with varied inputs automatically.
- Repeat count controls how many tests run.

Full Transcript

This example shows how a Verilog testbench uses a repeat loop to generate random inputs for signals 'a' and 'b' using the $random function. Each iteration assigns new random values, waits 10 time units, then repeats. The execution table traces each iteration's values and delay. Variables 'a' and 'b' change every iteration due to $random. The delay allows the device under test to respond before new inputs. The loop stops after 5 iterations as controlled by repeat(5). This method helps test hardware designs with varied inputs automatically.

Practice

1. What is the main purpose of using randomized test stimulus in Verilog testbenches?

easy

A. To manually set fixed input values for testing

B. To automatically test the design with many different input values

C. To speed up synthesis of the design

D. To generate clock signals for the design

Solution

1. Step 1: Understand randomized test stimulus

   Randomized test stimulus means giving the design many different input values automatically.

2. Step 2: Identify the purpose

   This helps find bugs by testing many cases without writing each one manually.

3. Final Answer:

   To automatically test the design with many different input values -> Option B

4. Quick Check:

   Randomized testing = automatic varied inputs [OK]

Hint: Random stimulus means many inputs tested automatically [OK]

Common Mistakes:

• Thinking it sets fixed inputs manually
• Confusing with clock generation
• Assuming it speeds synthesis

2. Which of the following is the correct syntax to generate a random number between 0 and 15 in Verilog?

easy

A. random(0, 15)

B. $random(0, 15)

C. $urandom(0, 15)

D. $urandom_range(0, 15)

Solution

1. Step 1: Recall Verilog random functions

   $urandom_range(min, max) generates a random number between min and max inclusive.

2. Step 2: Check options

   Only $urandom_range(0, 15) uses $urandom_range with correct syntax and parameters.

3. Final Answer:

   $urandom_range(0, 15) -> Option D

4. Quick Check:

   $urandom_range(min, max) = correct syntax [OK]

Hint: Use $urandom_range(min, max) for bounded random numbers [OK]

Common Mistakes:

• Using $random with parameters (wrong syntax)
• Using random without $ sign
• Using $urandom without range

3. Given the following Verilog code snippet inside an initial block:

reg [3:0] data;
initial begin
  data = $urandom_range(0, 15);
  $display("Data = %d", data);
end

What is the expected output?

medium

A. Data = a random number between 0 and 15

B. Data = 0

C. Data = 15

D. Syntax error

Solution

1. Step 1: Understand $urandom_range usage

   $urandom_range(0, 15) returns a random integer from 0 to 15 inclusive.

2. Step 2: Analyze $display output

   The $display prints the value of data, which is the random number assigned.

3. Final Answer:

   Data = a random number between 0 and 15 -> Option A

4. Quick Check:

   Random assignment prints random value [OK]

Hint: Random range assigns varied values printed by $display [OK]

Common Mistakes:

• Assuming fixed value 0 or 15
• Expecting syntax error
• Confusing $urandom_range with $random

4. Identify the error in this Verilog code snippet for random stimulus:

reg [7:0] input_signal;
initial begin
  input_signal = $urandom_range(255);
end

medium

A. Missing second argument in $urandom_range

B. input_signal should be wire, not reg

C. initial block cannot assign values

D. Syntax is correct, no error

Solution

1. Step 1: Check $urandom_range usage

   $urandom_range requires two arguments: minimum and maximum values.

2. Step 2: Identify missing argument

   Code uses only one argument (255), missing the minimum value.

3. Final Answer:

   Missing second argument in $urandom_range -> Option A

4. Quick Check:

   $urandom_range needs min and max [OK]

Hint: $urandom_range needs two numbers: min and max [OK]

Common Mistakes:

• Using only one argument in $urandom_range
• Thinking reg cannot be assigned in initial
• Confusing reg and wire usage

5. You want to test a 4-bit input signal with random values between 3 and 12 repeatedly every 10 time units. Which Verilog code snippet correctly implements this randomized test stimulus?

hard

A. always #10 input_signal = $urandom_range(3, 12)

B. always @(posedge clk) input_signal = $urandom_range(3, 12);

C. initial begin
forever #10 input_signal = $urandom_range(3, 12);
end

D. initial input_signal = $urandom_range(3, 12);

Solution

1. Step 1: Understand repeated random assignment every 10 time units

   Using initial with forever loop and delay #10 repeats the assignment continuously.

2. Step 2: Check options

   The always #10 option causes syntax issues due to improper structure.
   The @(posedge clk) option triggers on clock edges instead of time delays.
   The simple initial option assigns only once.
   The initial begin forever #10 option correctly repeats every 10 time units.

3. Final Answer:

   initial begin forever #10 input_signal = $urandom_range(3, 12); end -> Option C

4. Quick Check:

   Use initial + forever + #delay for repeated random stimulus [OK]

Hint: Use initial with forever and #delay for repeated random inputs [OK]

Common Mistakes:

• Using always without begin-end block
• Assigning only once in initial
• Confusing clock edge with time delay