Randomized test stimulus in Verilog - Mini Project: Build & Apply

Randomized Test Stimulus in Verilog

📖 Scenario: You are testing a simple digital module that adds two 4-bit numbers. To check if it works correctly, you want to create a testbench that sends random inputs to the module.

🎯 Goal: Build a Verilog testbench that generates random 4-bit inputs for two signals, applies them to the adder module, and displays the inputs and output.

📋 What You'll Learn

Create two 4-bit registers a and b to hold inputs

Create a wire sum to hold the output from the adder module

Add a clock signal clk toggling every 5 time units

Generate random values for a and b on every positive clock edge

Display the values of a, b, and sum each time inputs change

💡 Why This Matters

🌍 Real World

Randomized test stimulus helps verify digital circuits by testing many input combinations automatically, saving time and catching bugs early.

💼 Career

Hardware engineers and verification engineers use randomized testbenches to ensure their designs work correctly before manufacturing.

1

Create input and output signals

Create two 4-bit registers called a and b, and a 5-bit wire called sum.

Verilog

// Declare 4-bit registers a and b
// Declare 5-bit wire sum

Hint

Use reg [3:0] a; and reg [3:0] b; for inputs, and wire [4:0] sum; for output.

2

Add clock signal and instantiate adder module

Add a clock signal clk as a reg and initialize it to 0. Instantiate the adder module named adder_inst connecting a, b, and sum.

Verilog

reg [3:0] a;
reg [3:0] b;
wire [4:0] sum;
// Declare reg clk and initialize to 0
// Instantiate adder module adder_inst with ports a, b, sum

Hint

Use reg clk = 0; and instantiate the adder with named port connections.

3

Generate clock and random inputs

Create an always block that toggles clk every 5 time units. Create another always block triggered on the positive edge of clk that assigns random 4-bit values to a and b using $random.

Verilog

reg [3:0] a;
reg [3:0] b;
wire [4:0] sum;
reg clk = 0;

adder adder_inst(.a(a), .b(b), .sum(sum));

// Always block to toggle clk every 5 time units
// Always block on posedge clk to assign random values to a and b

Hint

Use always #5 clk = ~clk; for clock toggling and always @(posedge clk) for random input assignment.

4

Display inputs and output

Add an always block triggered on the positive edge of clk that uses $display to print the values of a, b, and sum in binary format.

Verilog

reg [3:0] a;
reg [3:0] b;
wire [4:0] sum;
reg clk = 0;

adder adder_inst(.a(a), .b(b), .sum(sum));

always #5 clk = ~clk;

always @(posedge clk) begin
    a <= $random % 16;
    b <= $random % 16;
end

// Always block on posedge clk to display a, b, sum

Hint

Use $display("a = %b, b = %b, sum = %b", a, b, sum); inside an always block triggered on posedge clk.

Practice

1. What is the main purpose of using randomized test stimulus in Verilog testbenches?

easy

A. To manually set fixed input values for testing

B. To automatically test the design with many different input values

C. To speed up synthesis of the design

D. To generate clock signals for the design

Solution

1. Step 1: Understand randomized test stimulus

   Randomized test stimulus means giving the design many different input values automatically.

2. Step 2: Identify the purpose

   This helps find bugs by testing many cases without writing each one manually.

3. Final Answer:

   To automatically test the design with many different input values -> Option B

4. Quick Check:

   Randomized testing = automatic varied inputs [OK]

Hint: Random stimulus means many inputs tested automatically [OK]

Common Mistakes:

• Thinking it sets fixed inputs manually
• Confusing with clock generation
• Assuming it speeds synthesis

2. Which of the following is the correct syntax to generate a random number between 0 and 15 in Verilog?

easy

A. random(0, 15)

B. $random(0, 15)

C. $urandom(0, 15)

D. $urandom_range(0, 15)

Solution

1. Step 1: Recall Verilog random functions

   $urandom_range(min, max) generates a random number between min and max inclusive.

2. Step 2: Check options

   Only $urandom_range(0, 15) uses $urandom_range with correct syntax and parameters.

3. Final Answer:

   $urandom_range(0, 15) -> Option D

4. Quick Check:

   $urandom_range(min, max) = correct syntax [OK]

Hint: Use $urandom_range(min, max) for bounded random numbers [OK]

Common Mistakes:

• Using $random with parameters (wrong syntax)
• Using random without $ sign
• Using $urandom without range

3. Given the following Verilog code snippet inside an initial block:

reg [3:0] data;
initial begin
  data = $urandom_range(0, 15);
  $display("Data = %d", data);
end

What is the expected output?

medium

A. Data = a random number between 0 and 15

B. Data = 0

C. Data = 15

D. Syntax error

Solution

1. Step 1: Understand $urandom_range usage

   $urandom_range(0, 15) returns a random integer from 0 to 15 inclusive.

2. Step 2: Analyze $display output

   The $display prints the value of data, which is the random number assigned.

3. Final Answer:

   Data = a random number between 0 and 15 -> Option A

4. Quick Check:

   Random assignment prints random value [OK]

Hint: Random range assigns varied values printed by $display [OK]

Common Mistakes:

• Assuming fixed value 0 or 15
• Expecting syntax error
• Confusing $urandom_range with $random

4. Identify the error in this Verilog code snippet for random stimulus:

reg [7:0] input_signal;
initial begin
  input_signal = $urandom_range(255);
end

medium

A. Missing second argument in $urandom_range

B. input_signal should be wire, not reg

C. initial block cannot assign values

D. Syntax is correct, no error

Solution

1. Step 1: Check $urandom_range usage

   $urandom_range requires two arguments: minimum and maximum values.

2. Step 2: Identify missing argument

   Code uses only one argument (255), missing the minimum value.

3. Final Answer:

   Missing second argument in $urandom_range -> Option A

4. Quick Check:

   $urandom_range needs min and max [OK]

Hint: $urandom_range needs two numbers: min and max [OK]

Common Mistakes:

• Using only one argument in $urandom_range
• Thinking reg cannot be assigned in initial
• Confusing reg and wire usage

5. You want to test a 4-bit input signal with random values between 3 and 12 repeatedly every 10 time units. Which Verilog code snippet correctly implements this randomized test stimulus?

hard

A. always #10 input_signal = $urandom_range(3, 12)

B. always @(posedge clk) input_signal = $urandom_range(3, 12);

C. initial begin
forever #10 input_signal = $urandom_range(3, 12);
end

D. initial input_signal = $urandom_range(3, 12);

Solution

1. Step 1: Understand repeated random assignment every 10 time units

   Using initial with forever loop and delay #10 repeats the assignment continuously.

2. Step 2: Check options

   The always #10 option causes syntax issues due to improper structure.
   The @(posedge clk) option triggers on clock edges instead of time delays.
   The simple initial option assigns only once.
   The initial begin forever #10 option correctly repeats every 10 time units.

3. Final Answer:

   initial begin forever #10 input_signal = $urandom_range(3, 12); end -> Option C

4. Quick Check:

   Use initial + forever + #delay for repeated random stimulus [OK]

Hint: Use initial with forever and #delay for repeated random inputs [OK]

Common Mistakes:

• Using always without begin-end block
• Assigning only once in initial
• Confusing clock edge with time delay