Randomized test stimulus in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of randomized test stimulus in Verilog?

Randomized test stimulus helps to generate varied and unpredictable input patterns to thoroughly test a design, increasing the chance of finding bugs.

beginner

How do you declare a random variable in SystemVerilog for test stimulus?

Use the rand keyword before the variable type, for example: rand bit [7:0] data; declares an 8-bit random variable.

intermediate

What is the role of the randomize() method in randomized testing?

It triggers the randomization process for variables declared with rand, assigning them new random values each time it is called.

intermediate

Why is it important to constrain random variables in test stimulus?

Constraints limit the range or conditions of random values to realistic or valid inputs, preventing invalid test cases and focusing testing on meaningful scenarios.

intermediate

Give an example of a simple constraint for a random variable in SystemVerilog.

For example, to constrain an 8-bit random variable data to values between 10 and 100:

constraint data_range { data >= 10; data <= 100; }

Which keyword is used to declare a random variable in SystemVerilog?

A rand

B random

C var

D randomize

The rand keyword declares a variable as randomizable in SystemVerilog.

What does the randomize() method do?

A Declares a variable as random

B Assigns random values to variables declared with <code>rand</code>

C Checks if a variable is random

D Disables randomization

Calling randomize() assigns new random values to rand variables.

Why should random variables be constrained?

A To increase simulation speed

B To make variables constant

C To disable randomization

D To limit values to valid ranges

Constraints ensure random values stay within valid or meaningful ranges.

Which of these is a valid constraint syntax in SystemVerilog?

A constraint c = var > 0 && var < 10;

B constraint c (var > 0 && var < 10);

C constraint c { var > 0; var < 10; }

D constraint c var > 0; var < 10;

Constraints are declared inside curly braces with semicolon-separated conditions.

What is the main benefit of using randomized test stimulus?

A To find bugs by testing many input combinations

B To make code run faster

C To reduce code size

D To avoid writing testbenches

Randomized stimulus helps uncover bugs by testing diverse inputs.

Explain how randomized test stimulus improves hardware verification.

Think about how random inputs help test more cases than fixed inputs.

Describe the steps to create and use a random variable in SystemVerilog testbench.

Focus on declaration, constraints, randomization, and usage.

Practice

1. What is the main purpose of using randomized test stimulus in Verilog testbenches?

easy

A. To manually set fixed input values for testing

B. To automatically test the design with many different input values

C. To speed up synthesis of the design

D. To generate clock signals for the design

Solution

1. Step 1: Understand randomized test stimulus

   Randomized test stimulus means giving the design many different input values automatically.

2. Step 2: Identify the purpose

   This helps find bugs by testing many cases without writing each one manually.

3. Final Answer:

   To automatically test the design with many different input values -> Option B

4. Quick Check:

   Randomized testing = automatic varied inputs [OK]

Hint: Random stimulus means many inputs tested automatically [OK]

Common Mistakes:

• Thinking it sets fixed inputs manually
• Confusing with clock generation
• Assuming it speeds synthesis

2. Which of the following is the correct syntax to generate a random number between 0 and 15 in Verilog?

easy

A. random(0, 15)

B. $random(0, 15)

C. $urandom(0, 15)

D. $urandom_range(0, 15)

Solution

1. Step 1: Recall Verilog random functions

   $urandom_range(min, max) generates a random number between min and max inclusive.

2. Step 2: Check options

   Only $urandom_range(0, 15) uses $urandom_range with correct syntax and parameters.

3. Final Answer:

   $urandom_range(0, 15) -> Option D

4. Quick Check:

   $urandom_range(min, max) = correct syntax [OK]

Hint: Use $urandom_range(min, max) for bounded random numbers [OK]

Common Mistakes:

• Using $random with parameters (wrong syntax)
• Using random without $ sign
• Using $urandom without range

3. Given the following Verilog code snippet inside an initial block:

reg [3:0] data;
initial begin
  data = $urandom_range(0, 15);
  $display("Data = %d", data);
end

What is the expected output?

medium

A. Data = a random number between 0 and 15

B. Data = 0

C. Data = 15

D. Syntax error

Solution

1. Step 1: Understand $urandom_range usage

   $urandom_range(0, 15) returns a random integer from 0 to 15 inclusive.

2. Step 2: Analyze $display output

   The $display prints the value of data, which is the random number assigned.

3. Final Answer:

   Data = a random number between 0 and 15 -> Option A

4. Quick Check:

   Random assignment prints random value [OK]

Hint: Random range assigns varied values printed by $display [OK]

Common Mistakes:

• Assuming fixed value 0 or 15
• Expecting syntax error
• Confusing $urandom_range with $random

4. Identify the error in this Verilog code snippet for random stimulus:

reg [7:0] input_signal;
initial begin
  input_signal = $urandom_range(255);
end

medium

A. Missing second argument in $urandom_range

B. input_signal should be wire, not reg

C. initial block cannot assign values

D. Syntax is correct, no error

Solution

1. Step 1: Check $urandom_range usage

   $urandom_range requires two arguments: minimum and maximum values.

2. Step 2: Identify missing argument

   Code uses only one argument (255), missing the minimum value.

3. Final Answer:

   Missing second argument in $urandom_range -> Option A

4. Quick Check:

   $urandom_range needs min and max [OK]

Hint: $urandom_range needs two numbers: min and max [OK]

Common Mistakes:

• Using only one argument in $urandom_range
• Thinking reg cannot be assigned in initial
• Confusing reg and wire usage

5. You want to test a 4-bit input signal with random values between 3 and 12 repeatedly every 10 time units. Which Verilog code snippet correctly implements this randomized test stimulus?

hard

A. always #10 input_signal = $urandom_range(3, 12)

B. always @(posedge clk) input_signal = $urandom_range(3, 12);

C. initial begin
forever #10 input_signal = $urandom_range(3, 12);
end

D. initial input_signal = $urandom_range(3, 12);

Solution

1. Step 1: Understand repeated random assignment every 10 time units

   Using initial with forever loop and delay #10 repeats the assignment continuously.

2. Step 2: Check options

   The always #10 option causes syntax issues due to improper structure.
   The @(posedge clk) option triggers on clock edges instead of time delays.
   The simple initial option assigns only once.
   The initial begin forever #10 option correctly repeats every 10 time units.

3. Final Answer:

   initial begin forever #10 input_signal = $urandom_range(3, 12); end -> Option C

4. Quick Check:

   Use initial + forever + #delay for repeated random stimulus [OK]

Hint: Use initial with forever and #delay for repeated random inputs [OK]

Common Mistakes:

• Using always without begin-end block
• Assigning only once in initial
• Confusing clock edge with time delay