Randomized test stimulus in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog testbench snippet?

Consider the following Verilog code that uses a random stimulus generator inside an initial block. What will be the value of data after 5 time units?

Verilog

module tb;
  reg clk = 0;
  reg [3:0] data;
  initial begin
    data = 4'b0000;
    #5;
    data = $urandom_range(0, 15);
  end
  always #1 clk = ~clk;
endmodule

A data will be a random 4-bit value between 0 and 15 after 5 time units

B data will remain undefined (X) after 5 time units

C data will be 4'b1111 after 5 time units

D data will always be 4'b0000 because $urandom_range is not synthesizable

💡 Hint

Think about what $urandom_range does inside an initial block in simulation.

The $urandom_range(0, 15) function generates a random integer between 0 and 15 inclusive. Since data is assigned this value after 5 time units, it will hold a random 4-bit value in that range.

🧠 Conceptual

intermediate

Which statement about randomized test stimulus in Verilog is true?

Choose the correct statement about using randomized stimulus in Verilog testbenches.

A Randomized stimulus can only be generated using <code>$random</code> and not <code>$urandom</code>.

B Randomized stimulus helps to test multiple input scenarios automatically without manual input changes.

C Randomized stimulus always produces the same sequence of values every simulation run.

D Randomized stimulus is synthesizable and can be used in hardware design.

💡 Hint

Think about the purpose of random stimulus in testbenches.

Randomized stimulus is used in testbenches to automatically generate different input values to test various scenarios. It is not synthesizable and $urandom is preferred over $random for better randomness. The sequence can be different each run unless seeded.

🔧 Debug

advanced

Why does this randomized test stimulus code produce the same sequence every run?

Examine the following Verilog code snippet used in a testbench:

initial begin
  integer seed = 12345;
  for (int i = 0; i < 5; i++) begin
    data[i] = $urandom(seed) % 16;
  end
end

Why does this code produce the same random sequence every simulation run?

A Because the seed variable is fixed and passed to <code>$urandom</code>, causing repeatable sequences.

B Because <code>$urandom</code> ignores the seed argument and always produces the same sequence.

C Because the modulus operator (%) limits randomness to zero only.

D Because the loop variable <code>i</code> is not declared correctly.

💡 Hint

Consider how seeding affects pseudo-random number generators.

Passing a fixed seed to $urandom causes it to generate the same sequence of random numbers every time, which is useful for repeatable tests.

📝 Syntax

advanced

Identify the syntax error in this randomized stimulus code

What is the syntax error in the following Verilog code snippet?

initial begin
  reg [3:0] data;
  data = $urandom_range(0, 15)
end

A The <code>reg</code> declaration cannot be inside an initial block.

B The function <code>$urandom_range</code> requires three arguments.

C The <code>initial</code> block must have a sensitivity list.

D Missing semicolon after the <code>$urandom_range</code> assignment.

💡 Hint

Check the end of each statement carefully.

In Verilog, each statement must end with a semicolon. The assignment to data is missing a semicolon.

🚀 Application

expert

How many unique 4-bit values can this randomized stimulus generate?

Given the following Verilog code snippet generating random 4-bit values:

initial begin
  for (int i = 0; i < 10; i++) begin
    data = $urandom_range(0, 15);
    #1;
  end
end

How many unique 4-bit values can data take during this loop?

A 4 unique values, since data is 4 bits wide

B 10 unique values, one per loop iteration

C 16 unique values, from 0 to 15 inclusive

D Only 1 unique value, because $urandom_range is seeded

💡 Hint

Consider the range of $urandom_range(0, 15) and the bit width of data.

The function $urandom_range(0, 15) can produce any integer from 0 to 15 inclusive, which fits exactly in 4 bits. So data can take 16 unique values.

Practice

1. What is the main purpose of using randomized test stimulus in Verilog testbenches?

easy

A. To manually set fixed input values for testing

B. To automatically test the design with many different input values

C. To speed up synthesis of the design

D. To generate clock signals for the design

Solution

1. Step 1: Understand randomized test stimulus

   Randomized test stimulus means giving the design many different input values automatically.

2. Step 2: Identify the purpose

   This helps find bugs by testing many cases without writing each one manually.

3. Final Answer:

   To automatically test the design with many different input values -> Option B

4. Quick Check:

   Randomized testing = automatic varied inputs [OK]

Hint: Random stimulus means many inputs tested automatically [OK]

Common Mistakes:

• Thinking it sets fixed inputs manually
• Confusing with clock generation
• Assuming it speeds synthesis

2. Which of the following is the correct syntax to generate a random number between 0 and 15 in Verilog?

easy

A. random(0, 15)

B. $random(0, 15)

C. $urandom(0, 15)

D. $urandom_range(0, 15)

Solution

1. Step 1: Recall Verilog random functions

   $urandom_range(min, max) generates a random number between min and max inclusive.

2. Step 2: Check options

   Only $urandom_range(0, 15) uses $urandom_range with correct syntax and parameters.

3. Final Answer:

   $urandom_range(0, 15) -> Option D

4. Quick Check:

   $urandom_range(min, max) = correct syntax [OK]

Hint: Use $urandom_range(min, max) for bounded random numbers [OK]

Common Mistakes:

• Using $random with parameters (wrong syntax)
• Using random without $ sign
• Using $urandom without range

3. Given the following Verilog code snippet inside an initial block:

reg [3:0] data;
initial begin
  data = $urandom_range(0, 15);
  $display("Data = %d", data);
end

What is the expected output?

medium

A. Data = a random number between 0 and 15

B. Data = 0

C. Data = 15

D. Syntax error

Solution

1. Step 1: Understand $urandom_range usage

   $urandom_range(0, 15) returns a random integer from 0 to 15 inclusive.

2. Step 2: Analyze $display output

   The $display prints the value of data, which is the random number assigned.

3. Final Answer:

   Data = a random number between 0 and 15 -> Option A

4. Quick Check:

   Random assignment prints random value [OK]

Hint: Random range assigns varied values printed by $display [OK]

Common Mistakes:

• Assuming fixed value 0 or 15
• Expecting syntax error
• Confusing $urandom_range with $random

4. Identify the error in this Verilog code snippet for random stimulus:

reg [7:0] input_signal;
initial begin
  input_signal = $urandom_range(255);
end

medium

A. Missing second argument in $urandom_range

B. input_signal should be wire, not reg

C. initial block cannot assign values

D. Syntax is correct, no error

Solution

1. Step 1: Check $urandom_range usage

   $urandom_range requires two arguments: minimum and maximum values.

2. Step 2: Identify missing argument

   Code uses only one argument (255), missing the minimum value.

3. Final Answer:

   Missing second argument in $urandom_range -> Option A

4. Quick Check:

   $urandom_range needs min and max [OK]

Hint: $urandom_range needs two numbers: min and max [OK]

Common Mistakes:

• Using only one argument in $urandom_range
• Thinking reg cannot be assigned in initial
• Confusing reg and wire usage

5. You want to test a 4-bit input signal with random values between 3 and 12 repeatedly every 10 time units. Which Verilog code snippet correctly implements this randomized test stimulus?

hard

A. always #10 input_signal = $urandom_range(3, 12)

B. always @(posedge clk) input_signal = $urandom_range(3, 12);

C. initial begin
forever #10 input_signal = $urandom_range(3, 12);
end

D. initial input_signal = $urandom_range(3, 12);

Solution

1. Step 1: Understand repeated random assignment every 10 time units

   Using initial with forever loop and delay #10 repeats the assignment continuously.

2. Step 2: Check options

   The always #10 option causes syntax issues due to improper structure.
   The @(posedge clk) option triggers on clock edges instead of time delays.
   The simple initial option assigns only once.
   The initial begin forever #10 option correctly repeats every 10 time units.

3. Final Answer:

   initial begin forever #10 input_signal = $urandom_range(3, 12); end -> Option C

4. Quick Check:

   Use initial + forever + #delay for repeated random stimulus [OK]

Hint: Use initial with forever and #delay for repeated random inputs [OK]

Common Mistakes:

• Using always without begin-end block
• Assigning only once in initial
• Confusing clock edge with time delay