Randomized test stimulus in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a random variable in SystemVerilog.

Verilog

rand bit [1];

Drag options to blanks, or click blank then click option'

Areset

Bclk

Cdata

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or reset as random variable names.

Forgetting to declare the variable as rand.

The keyword rand declares a random variable named data.

2fill in blank

medium

Complete the code to generate a random value for the variable.

Verilog

assert([1].randomize());

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Adata

Benable

Creset

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Calling randomize on non-random variables.

Using signals like clk or reset instead of the random variable.

The randomize() method is called on the random variable data to generate a new random value.

3fill in blank

hard

Fix the error in the code to constrain the random variable to values less than 10.

Verilog

constraint data_limit { [1] < 10; }

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Aclk

Benable

Creset

Ddata

Attempts:

3 left

💡 Hint

Common Mistakes

Using signal names instead of the random variable in constraints.

Syntax errors in constraint declaration.

The constraint must refer to the random variable data to limit its values.

4fill in blank

hard

Fill both blanks to declare a class with a random variable and a constraint.

Verilog

class RandomGen;
  rand bit [1];
  constraint [2]_limit { [1] < 16; }
endclass

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Avalue

Bclk

Cdata

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Mismatch between variable and constraint names.

Using signal names instead of variable names.

The random variable is named value, and the constraint is named value_limit to match.

5fill in blank

hard

Fill all three blanks to create a testbench that randomizes a variable and displays its value.

Verilog

module testbench;
  [1] rand_var;
  initial begin
    rand_var = new();
    if (rand_var.[2]()) begin
      $display("Random value: %0d", rand_var.[3]);
    end
  end
endmodule

Drag options to blanks, or click blank then click option'

ARandomGen

Brandomize

Cvalue

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using signal names instead of class or variable names.

Forgetting to call randomize before displaying.

The module declares an instance of class RandomGen, calls randomize() to generate a value, and displays the value variable.

Practice

1. What is the main purpose of using randomized test stimulus in Verilog testbenches?

easy

A. To manually set fixed input values for testing

B. To automatically test the design with many different input values

C. To speed up synthesis of the design

D. To generate clock signals for the design

Solution

1. Step 1: Understand randomized test stimulus

   Randomized test stimulus means giving the design many different input values automatically.

2. Step 2: Identify the purpose

   This helps find bugs by testing many cases without writing each one manually.

3. Final Answer:

   To automatically test the design with many different input values -> Option B

4. Quick Check:

   Randomized testing = automatic varied inputs [OK]

Hint: Random stimulus means many inputs tested automatically [OK]

Common Mistakes:

• Thinking it sets fixed inputs manually
• Confusing with clock generation
• Assuming it speeds synthesis

2. Which of the following is the correct syntax to generate a random number between 0 and 15 in Verilog?

easy

A. random(0, 15)

B. $random(0, 15)

C. $urandom(0, 15)

D. $urandom_range(0, 15)

Solution

1. Step 1: Recall Verilog random functions

   $urandom_range(min, max) generates a random number between min and max inclusive.

2. Step 2: Check options

   Only $urandom_range(0, 15) uses $urandom_range with correct syntax and parameters.

3. Final Answer:

   $urandom_range(0, 15) -> Option D

4. Quick Check:

   $urandom_range(min, max) = correct syntax [OK]

Hint: Use $urandom_range(min, max) for bounded random numbers [OK]

Common Mistakes:

• Using $random with parameters (wrong syntax)
• Using random without $ sign
• Using $urandom without range

3. Given the following Verilog code snippet inside an initial block:

reg [3:0] data;
initial begin
  data = $urandom_range(0, 15);
  $display("Data = %d", data);
end

What is the expected output?

medium

A. Data = a random number between 0 and 15

B. Data = 0

C. Data = 15

D. Syntax error

Solution

1. Step 1: Understand $urandom_range usage

   $urandom_range(0, 15) returns a random integer from 0 to 15 inclusive.

2. Step 2: Analyze $display output

   The $display prints the value of data, which is the random number assigned.

3. Final Answer:

   Data = a random number between 0 and 15 -> Option A

4. Quick Check:

   Random assignment prints random value [OK]

Hint: Random range assigns varied values printed by $display [OK]

Common Mistakes:

• Assuming fixed value 0 or 15
• Expecting syntax error
• Confusing $urandom_range with $random

4. Identify the error in this Verilog code snippet for random stimulus:

reg [7:0] input_signal;
initial begin
  input_signal = $urandom_range(255);
end

medium

A. Missing second argument in $urandom_range

B. input_signal should be wire, not reg

C. initial block cannot assign values

D. Syntax is correct, no error

Solution

1. Step 1: Check $urandom_range usage

   $urandom_range requires two arguments: minimum and maximum values.

2. Step 2: Identify missing argument

   Code uses only one argument (255), missing the minimum value.

3. Final Answer:

   Missing second argument in $urandom_range -> Option A

4. Quick Check:

   $urandom_range needs min and max [OK]

Hint: $urandom_range needs two numbers: min and max [OK]

Common Mistakes:

• Using only one argument in $urandom_range
• Thinking reg cannot be assigned in initial
• Confusing reg and wire usage

5. You want to test a 4-bit input signal with random values between 3 and 12 repeatedly every 10 time units. Which Verilog code snippet correctly implements this randomized test stimulus?

hard

A. always #10 input_signal = $urandom_range(3, 12)

B. always @(posedge clk) input_signal = $urandom_range(3, 12);

C. initial begin
forever #10 input_signal = $urandom_range(3, 12);
end

D. initial input_signal = $urandom_range(3, 12);

Solution

1. Step 1: Understand repeated random assignment every 10 time units

   Using initial with forever loop and delay #10 repeats the assignment continuously.

2. Step 2: Check options

   The always #10 option causes syntax issues due to improper structure.
   The @(posedge clk) option triggers on clock edges instead of time delays.
   The simple initial option assigns only once.
   The initial begin forever #10 option correctly repeats every 10 time units.

3. Final Answer:

   initial begin forever #10 input_signal = $urandom_range(3, 12); end -> Option C

4. Quick Check:

   Use initial + forever + #delay for repeated random stimulus [OK]

Hint: Use initial with forever and #delay for repeated random inputs [OK]

Common Mistakes:

• Using always without begin-end block
• Assigning only once in initial
• Confusing clock edge with time delay