Code coverage concepts in Verilog - Step-by-Step Execution

Concept Flow - Code coverage concepts

Start Simulation

↓

Stimulus Applied

↓

Code Executes

↓

Coverage Points Hit?

No→Record Miss

Yes↓

Record Coverage

↓

All Tests Done?

No→Apply More Stimulus

Yes↓

Generate Coverage Report

↓

Analyze & Improve Tests

↓

End

This flow shows how simulation runs, coverage points are checked and recorded, and reports are generated to improve test quality.

Execution Sample

Verilog

covergroup cg;
  coverpoint signal;
endgroup

cg cg_inst = new();

initial begin
  cg_inst.sample();
end

This simple Verilog code defines a coverage group and samples a signal to track coverage during simulation.

Execution Table

Step	Action	Coverage Point	Coverage Hit?	Coverage Recorded
1	Start simulation	N/A	N/A	No
2	Apply stimulus: signal=0	signal=0	Yes	Yes
3	Apply stimulus: signal=1	signal=1	Yes	Yes
4	Apply stimulus: signal=0	signal=0	Already hit	No new record
5	Check if all coverage points hit	signal=0 and signal=1	Yes	Coverage complete
6	Generate coverage report	N/A	N/A	Report shows 100% coverage
7	End simulation	N/A	N/A	No

💡 Simulation ends after all coverage points are hit and report is generated.

Variable Tracker

Variable	Start	After Step 2	After Step 3	After Step 4	Final
signal	undefined	0	1	0	0
coverage_signal_0	No	Yes	Yes	Yes	Yes
coverage_signal_1	No	No	Yes	Yes	Yes

Key Moments - 2 Insights

Why does coverage_signal_0 not record a new hit at step 4 even though signal=0 again?

Because coverage points record hits only once per unique condition; step 4 repeats signal=0 which was already covered at step 2, so no new coverage is recorded.

What happens if some coverage points are never hit during simulation?

The coverage report will show those points as missed, indicating incomplete test coverage and the need for additional test stimulus.

Visual Quiz - 3 Questions

Look at the execution table, at which step is the coverage for signal=1 first recorded?

A Step 3

B Step 2

C Step 4

D Step 5

💡 Hint

Check the 'Coverage Hit?' column for signal=1 in the execution table.

According to the variable tracker, what is the value of coverage_signal_0 after step 3?

A No

B Yes

C Undefined

D No new record

💡 Hint

Look at the 'coverage_signal_0' row and the 'After Step 3' column in the variable tracker.

If the stimulus never sets signal=1, how would the coverage report change?

A It would show 100% coverage

B It would show coverage_signal_0 as missed

C It would show coverage_signal_1 as missed

D It would not generate a report

💡 Hint

Refer to the key moment about missed coverage points and the execution table coverage hits.

Concept Snapshot

Code coverage tracks which parts of your Verilog code run during simulation.
Use covergroups and coverpoints to define coverage points.
Simulation applies stimulus, coverage points record hits once per unique condition.
Coverage reports show which points were hit or missed.
Missed points mean tests need improvement.

Full Transcript

Code coverage in Verilog helps check which parts of your design are tested during simulation. You define coverage points using covergroups and coverpoints. When simulation runs and stimulus changes signals, coverage points record hits if conditions occur. Each unique condition is recorded once. The simulation continues until all coverage points are hit or tests end. A coverage report is generated showing which points were covered and which were missed. Missed coverage points mean you should add more tests to cover those parts. This process helps improve test quality and design confidence.

Practice

1. What is the main purpose of code coverage in Verilog simulations?

easy

A. To generate synthesis reports

B. To speed up the simulation runtime

C. To check which parts of the design have been tested

D. To optimize the hardware layout

Solution

1. Step 1: Understand code coverage concept

   Code coverage tracks which parts of the Verilog design are exercised during simulation.

2. Step 2: Identify the main goal

   The goal is to ensure tests cover all design parts, improving test quality.

3. Final Answer:

   To check which parts of the design have been tested -> Option C

4. Quick Check:

   Code coverage = tested parts check [OK]

Hint: Code coverage shows tested design parts, not speed or layout [OK]

Common Mistakes:

• Confusing coverage with simulation speed
• Thinking coverage generates synthesis reports
• Assuming coverage optimizes hardware layout

2. Which SystemVerilog construct is used to define a coverage point in code coverage?

easy

A. coverpoint

B. assertion

C. covergroup

D. property

Solution

1. Step 1: Recall coverage constructs

   SystemVerilog uses covergroup to group coverage points and coverpoint to define individual coverage points.

2. Step 2: Identify the coverage point

   The coverage point is specifically defined by coverpoint, inside a covergroup.

3. Final Answer:

   coverpoint -> Option A

4. Quick Check:

   Coverage point = coverpoint [OK]

Hint: Coverpoint defines coverage points inside covergroups [OK]

Common Mistakes:

• Confusing covergroup with coverpoint
• Using assertion or property for coverage points
• Mixing coverage with verification constructs

3. Given the following code snippet, what will be the coverage count for state after these values: 0, 1, 0, 2?

int state;
covergroup cg;
  coverpoint state;
endgroup

cg cg_inst = new();
state = 0;
cg_inst.sample();
state = 1;
cg_inst.sample();
state = 0;
cg_inst.sample();
state = 2;
cg_inst.sample();

medium

A. 1

B. 4

C. 2

D. 3

Solution

1. Step 1: Understand coverage counting

   Coverage counts unique values sampled by the coverpoint. Values 0,1,2 appear.

2. Step 2: Count unique values

   Values sampled: 0 (twice), 1, 2. Unique values are 0,1,2 -> 3 unique hits.

3. Final Answer:

   3 -> Option D

4. Quick Check:

   Unique states = 3 [OK]

Hint: Count unique sampled values for coverage count [OK]

Common Mistakes:

• Counting repeated samples multiple times
• Assuming total samples equal coverage count
• Ignoring unique value concept

4. Identify the error in this coverage code snippet:

int signal;
covergroup cg;
  coverpoint signal {
    bins low = {0};
    bins high = {1};
  }
endgroup

cg cg_inst = new();
signal = 2;
cg_inst.sample();

medium

A. Missing semicolon after coverpoint declaration

B. Bins do not cover the sampled value 2

C. covergroup must have a constructor

D. sample() method is not valid

Solution

1. Step 1: Analyze bins coverage

   Bins cover values 0 and 1 only. Sampled value is 2, which is not covered.

2. Step 2: Identify error impact

   Sampling 2 will not hit any bin, causing incomplete coverage.

3. Final Answer:

   Bins do not cover the sampled value 2 -> Option B

4. Quick Check:

   Bins coverage missing sampled value [OK]

Hint: Check if bins cover all sampled values [OK]

Common Mistakes:

• Ignoring uncovered sampled values
• Thinking semicolon is missing after coverpoint
• Assuming sample() method is invalid

5. How can you combine multiple coverpoints in a covergroup to track cross coverage of signals a and b in SystemVerilog?

hard

A. Define coverpoints for a and b and add a cross coverage for both inside the covergroup

B. Define separate covergroups for a and b without cross coverage

C. Use assertions to check a and b values

D. Sample a and b separately without grouping

Solution

1. Step 1: Understand covergroup composition

   A covergroup can contain multiple coverpoints to track individual signals.

2. Step 2: Use cross coverage

   Cross coverage tracks combinations of values from multiple coverpoints, here a and b.

3. Final Answer:

   Define coverpoints for a and b and add a cross coverage for both inside the covergroup -> Option A

4. Quick Check:

   Cross coverage = combined signal tracking [OK]

Hint: Use cross coverage inside covergroup for multiple signals [OK]

Common Mistakes:

• Not using cross coverage for combined signals
• Defining separate covergroups without cross
• Confusing assertions with coverage