Code coverage concepts in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this coverage report snippet?

Given the following coverage data snippet from a Verilog coverage report, what is the coverage percentage for the state variable?

state: 8 bins, 6 hit

A 75%

B 60%

C 66.67%

D 80%

💡 Hint

Coverage percentage = (bins hit / total bins) * 100

6 bins hit out of 8 total bins means coverage is (6/8)*100 = 75%. But 6/8 = 0.75 which is 75%. The correct option is 75%.

🧠 Conceptual

intermediate

Which coverage type measures if all possible input combinations were tested?

In Verilog code coverage, which type specifically checks that all combinations of input signals have been exercised?

A Toggle coverage

B Statement coverage

C Cross coverage

D Expression coverage

💡 Hint

Think about coverage that involves multiple signals combined.

Cross coverage tracks combinations of signals or variables to ensure all pairs or tuples of values occur. This checks input combinations.

🔧 Debug

advanced

What error does this coverage code cause?

Consider this Verilog coverage code snippet:

covergroup cg;
  coverpoint signal {
    bins low = {0};
    bins high = {1};
  }
endgroup

initial begin
  cg cg_inst = new();
  cg_inst.sample(signal);
end

What error will this code produce when simulated?

A TypeError: Cannot sample before covergroup instantiation

B SyntaxError: Missing semicolon after covergroup

C No error, code runs fine

D RuntimeError: 'signal' is undeclared or not in scope

💡 Hint

Check if signal is declared anywhere.

The variable signal is used but not declared anywhere in the code, causing a runtime error.

📝 Syntax

advanced

Which option correctly defines a covergroup with a coverpoint on 'opcode'?

Choose the correct Verilog code snippet that defines a covergroup named cg with a coverpoint on opcode signal.

A

covergroup cg;
  coverpoint opcode;
endgroup

B

covergroup cg (input logic [3:0] opcode);
  coverpoint opcode;
endgroup

C

covergroup cg;
  coverpoint opcode {
    bins opcodes[] = {[0:15]};
  }
endgroup

D

covergroup cg;
  coverpoint opcode {
    bins opcodes = {0,1,2,3,4};
  }
endgroup

💡 Hint

Check the syntax for parameterized covergroups.

Option B correctly declares a covergroup with an input argument and a coverpoint on that input.

🚀 Application

expert

How many bins are created by this cross coverage?

Given two coverpoints:

coverpoint a {
  bins a_bins = {0,1};
}
coverpoint b {
  bins b_bins = {0,1,2};
}

cross a, b;

How many bins does the cross coverage create?

A 6

B 2

C 3

D 5

💡 Hint

Multiply the number of bins in each coverpoint.

Cross coverage bins = number of bins in 'a' * number of bins in 'b' = 2 * 3 = 6.

Practice

1. What is the main purpose of code coverage in Verilog simulations?

easy

A. To generate synthesis reports

B. To speed up the simulation runtime

C. To check which parts of the design have been tested

D. To optimize the hardware layout

Solution

1. Step 1: Understand code coverage concept

   Code coverage tracks which parts of the Verilog design are exercised during simulation.

2. Step 2: Identify the main goal

   The goal is to ensure tests cover all design parts, improving test quality.

3. Final Answer:

   To check which parts of the design have been tested -> Option C

4. Quick Check:

   Code coverage = tested parts check [OK]

Hint: Code coverage shows tested design parts, not speed or layout [OK]

Common Mistakes:

• Confusing coverage with simulation speed
• Thinking coverage generates synthesis reports
• Assuming coverage optimizes hardware layout

2. Which SystemVerilog construct is used to define a coverage point in code coverage?

easy

A. coverpoint

B. assertion

C. covergroup

D. property

Solution

1. Step 1: Recall coverage constructs

   SystemVerilog uses covergroup to group coverage points and coverpoint to define individual coverage points.

2. Step 2: Identify the coverage point

   The coverage point is specifically defined by coverpoint, inside a covergroup.

3. Final Answer:

   coverpoint -> Option A

4. Quick Check:

   Coverage point = coverpoint [OK]

Hint: Coverpoint defines coverage points inside covergroups [OK]

Common Mistakes:

• Confusing covergroup with coverpoint
• Using assertion or property for coverage points
• Mixing coverage with verification constructs

3. Given the following code snippet, what will be the coverage count for state after these values: 0, 1, 0, 2?

int state;
covergroup cg;
  coverpoint state;
endgroup

cg cg_inst = new();
state = 0;
cg_inst.sample();
state = 1;
cg_inst.sample();
state = 0;
cg_inst.sample();
state = 2;
cg_inst.sample();

medium

A. 1

B. 4

C. 2

D. 3

Solution

1. Step 1: Understand coverage counting

   Coverage counts unique values sampled by the coverpoint. Values 0,1,2 appear.

2. Step 2: Count unique values

   Values sampled: 0 (twice), 1, 2. Unique values are 0,1,2 -> 3 unique hits.

3. Final Answer:

   3 -> Option D

4. Quick Check:

   Unique states = 3 [OK]

Hint: Count unique sampled values for coverage count [OK]

Common Mistakes:

• Counting repeated samples multiple times
• Assuming total samples equal coverage count
• Ignoring unique value concept

4. Identify the error in this coverage code snippet:

int signal;
covergroup cg;
  coverpoint signal {
    bins low = {0};
    bins high = {1};
  }
endgroup

cg cg_inst = new();
signal = 2;
cg_inst.sample();

medium

A. Missing semicolon after coverpoint declaration

B. Bins do not cover the sampled value 2

C. covergroup must have a constructor

D. sample() method is not valid

Solution

1. Step 1: Analyze bins coverage

   Bins cover values 0 and 1 only. Sampled value is 2, which is not covered.

2. Step 2: Identify error impact

   Sampling 2 will not hit any bin, causing incomplete coverage.

3. Final Answer:

   Bins do not cover the sampled value 2 -> Option B

4. Quick Check:

   Bins coverage missing sampled value [OK]

Hint: Check if bins cover all sampled values [OK]

Common Mistakes:

• Ignoring uncovered sampled values
• Thinking semicolon is missing after coverpoint
• Assuming sample() method is invalid

5. How can you combine multiple coverpoints in a covergroup to track cross coverage of signals a and b in SystemVerilog?

hard

A. Define coverpoints for a and b and add a cross coverage for both inside the covergroup

B. Define separate covergroups for a and b without cross coverage

C. Use assertions to check a and b values

D. Sample a and b separately without grouping

Solution

1. Step 1: Understand covergroup composition

   A covergroup can contain multiple coverpoints to track individual signals.

2. Step 2: Use cross coverage

   Cross coverage tracks combinations of values from multiple coverpoints, here a and b.

3. Final Answer:

   Define coverpoints for a and b and add a cross coverage for both inside the covergroup -> Option A

4. Quick Check:

   Cross coverage = combined signal tracking [OK]

Hint: Use cross coverage inside covergroup for multiple signals [OK]

Common Mistakes:

• Not using cross coverage for combined signals
• Defining separate covergroups without cross
• Confusing assertions with coverage