Code coverage concepts in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is code coverage in Verilog verification?

Code coverage measures how much of the Verilog design or testbench code has been exercised by the tests. It helps ensure that tests check all parts of the design.

beginner

Name the main types of code coverage used in Verilog verification.

The main types are:
1. Statement coverage
2. Branch coverage
3. Condition coverage
4. Toggle coverage
5. FSM coverage

beginner

What does statement coverage check?

Statement coverage checks if every line of code (statement) in the design or testbench has been executed at least once during simulation.

intermediate

Explain branch coverage with an example.

Branch coverage checks if every possible branch (like if-else paths) has been taken. For example, if you have an if statement, branch coverage ensures both the 'if' and 'else' parts run at least once.

intermediate

Why is toggle coverage important in hardware verification?

Toggle coverage checks if signals have changed value (0 to 1 or 1 to 0). It ensures that all bits in signals or registers have toggled, which is important to verify dynamic behavior.

Which type of coverage ensures every line of code is executed at least once?

A FSM coverage

B Branch coverage

C Toggle coverage

D Statement coverage

Statement coverage measures if each line of code has been run during simulation.

What does branch coverage verify in Verilog code?

A All possible decision paths

B All lines executed

C All signal toggles

D All finite state machine states

Branch coverage checks that every decision path (like if-else) has been taken.

Toggle coverage is mainly used to check:

A If signals change values

B If all code lines run

C If all branches are taken

D If all conditions are true

Toggle coverage ensures signals have switched between 0 and 1.

Which coverage type is best to verify all states in a finite state machine?

A Statement coverage

B Branch coverage

C FSM coverage

D Toggle coverage

FSM coverage checks that all states and transitions in a finite state machine are exercised.

Why is code coverage important in Verilog verification?

A To check syntax errors

B To ensure all code is tested

C To speed up simulation

D To reduce code size

Code coverage helps confirm that tests exercise all parts of the design.

Describe the different types of code coverage used in Verilog and what each type checks.

Think about lines, decisions, signal changes, and states.

Explain why code coverage is useful in hardware verification and how it helps improve test quality.

Consider how coverage relates to test thoroughness.

Practice

1. What is the main purpose of code coverage in Verilog simulations?

easy

A. To generate synthesis reports

B. To speed up the simulation runtime

C. To check which parts of the design have been tested

D. To optimize the hardware layout

Solution

1. Step 1: Understand code coverage concept

   Code coverage tracks which parts of the Verilog design are exercised during simulation.

2. Step 2: Identify the main goal

   The goal is to ensure tests cover all design parts, improving test quality.

3. Final Answer:

   To check which parts of the design have been tested -> Option C

4. Quick Check:

   Code coverage = tested parts check [OK]

Hint: Code coverage shows tested design parts, not speed or layout [OK]

Common Mistakes:

• Confusing coverage with simulation speed
• Thinking coverage generates synthesis reports
• Assuming coverage optimizes hardware layout

2. Which SystemVerilog construct is used to define a coverage point in code coverage?

easy

A. coverpoint

B. assertion

C. covergroup

D. property

Solution

1. Step 1: Recall coverage constructs

   SystemVerilog uses covergroup to group coverage points and coverpoint to define individual coverage points.

2. Step 2: Identify the coverage point

   The coverage point is specifically defined by coverpoint, inside a covergroup.

3. Final Answer:

   coverpoint -> Option A

4. Quick Check:

   Coverage point = coverpoint [OK]

Hint: Coverpoint defines coverage points inside covergroups [OK]

Common Mistakes:

• Confusing covergroup with coverpoint
• Using assertion or property for coverage points
• Mixing coverage with verification constructs

3. Given the following code snippet, what will be the coverage count for state after these values: 0, 1, 0, 2?

int state;
covergroup cg;
  coverpoint state;
endgroup

cg cg_inst = new();
state = 0;
cg_inst.sample();
state = 1;
cg_inst.sample();
state = 0;
cg_inst.sample();
state = 2;
cg_inst.sample();

medium

A. 1

B. 4

C. 2

D. 3

Solution

1. Step 1: Understand coverage counting

   Coverage counts unique values sampled by the coverpoint. Values 0,1,2 appear.

2. Step 2: Count unique values

   Values sampled: 0 (twice), 1, 2. Unique values are 0,1,2 -> 3 unique hits.

3. Final Answer:

   3 -> Option D

4. Quick Check:

   Unique states = 3 [OK]

Hint: Count unique sampled values for coverage count [OK]

Common Mistakes:

• Counting repeated samples multiple times
• Assuming total samples equal coverage count
• Ignoring unique value concept

4. Identify the error in this coverage code snippet:

int signal;
covergroup cg;
  coverpoint signal {
    bins low = {0};
    bins high = {1};
  }
endgroup

cg cg_inst = new();
signal = 2;
cg_inst.sample();

medium

A. Missing semicolon after coverpoint declaration

B. Bins do not cover the sampled value 2

C. covergroup must have a constructor

D. sample() method is not valid

Solution

1. Step 1: Analyze bins coverage

   Bins cover values 0 and 1 only. Sampled value is 2, which is not covered.

2. Step 2: Identify error impact

   Sampling 2 will not hit any bin, causing incomplete coverage.

3. Final Answer:

   Bins do not cover the sampled value 2 -> Option B

4. Quick Check:

   Bins coverage missing sampled value [OK]

Hint: Check if bins cover all sampled values [OK]

Common Mistakes:

• Ignoring uncovered sampled values
• Thinking semicolon is missing after coverpoint
• Assuming sample() method is invalid

5. How can you combine multiple coverpoints in a covergroup to track cross coverage of signals a and b in SystemVerilog?

hard

A. Define coverpoints for a and b and add a cross coverage for both inside the covergroup

B. Define separate covergroups for a and b without cross coverage

C. Use assertions to check a and b values

D. Sample a and b separately without grouping

Solution

1. Step 1: Understand covergroup composition

   A covergroup can contain multiple coverpoints to track individual signals.

2. Step 2: Use cross coverage

   Cross coverage tracks combinations of values from multiple coverpoints, here a and b.

3. Final Answer:

   Define coverpoints for a and b and add a cross coverage for both inside the covergroup -> Option A

4. Quick Check:

   Cross coverage = combined signal tracking [OK]

Hint: Use cross coverage inside covergroup for multiple signals [OK]

Common Mistakes:

• Not using cross coverage for combined signals
• Defining separate covergroups without cross
• Confusing assertions with coverage