Code coverage concepts in Verilog - Mini Project: Build & Apply

Code Coverage Concepts in Verilog

📖 Scenario: You are working on a simple digital design and want to check which parts of your code are tested during simulation. This helps you find untested parts and improve your tests.

🎯 Goal: Build a small Verilog module with some conditions and add code coverage points to see which parts run during simulation.

📋 What You'll Learn

Create a Verilog module with inputs and outputs

Add a configuration variable to control a threshold

Write conditional logic using if statements

Add code coverage points using covergroup and coverpoint

Simulate and print coverage results

💡 Why This Matters

🌍 Real World

Code coverage helps hardware engineers find parts of their design that are not tested well. This improves test quality and reduces bugs in chips.

💼 Career

Understanding code coverage is important for verification engineers and anyone working on hardware design validation.

1

Create a Verilog module with inputs and outputs

Write a Verilog module called threshold_checker with an input value (4 bits) and an output flag (1 bit).

Verilog

module threshold_checker(input [3:0] value, output reg flag);
// Your code here
endmodule

Hint

Define the module with the exact name and ports as described.

2

Add a configuration variable for threshold

Inside the threshold_checker module, declare a parameter called THRESHOLD and set it to 8.

Verilog

module threshold_checker(input [3:0] value, output reg flag);
    // Declare parameter THRESHOLD here
    // Your code here
endmodule

Hint

Use parameter THRESHOLD = 8; inside the module.

3

Add conditional logic to set the flag

Add an always block that sets flag to 1 if value is greater than THRESHOLD, else sets flag to 0.

Verilog

module threshold_checker(input [3:0] value, output reg flag);
    parameter THRESHOLD = 8;
    // Add always block with if condition here
    // Your code here
endmodule

Hint

Use an always @(*) block with an if statement comparing value and THRESHOLD.

4

Add code coverage points and print coverage

Add a covergroup named cg inside the module that covers the value input with a coverpoint. Instantiate and sample it inside the always block. Then add a initial block to print "Coverage collected".

Verilog

module threshold_checker(input [3:0] value, output reg flag);
    parameter THRESHOLD = 8;
    // Define covergroup cg with coverpoint for value
    // Instantiate cg and sample it inside always block
    // Add initial block to print coverage message
    // Your code here
endmodule

Hint

Define a covergroup with a coverpoint for value. Create an instance and call sample() inside the always block. Use $display in an initial block.

Practice

1. What is the main purpose of code coverage in Verilog simulations?

easy

A. To generate synthesis reports

B. To speed up the simulation runtime

C. To check which parts of the design have been tested

D. To optimize the hardware layout

Solution

1. Step 1: Understand code coverage concept

   Code coverage tracks which parts of the Verilog design are exercised during simulation.

2. Step 2: Identify the main goal

   The goal is to ensure tests cover all design parts, improving test quality.

3. Final Answer:

   To check which parts of the design have been tested -> Option C

4. Quick Check:

   Code coverage = tested parts check [OK]

Hint: Code coverage shows tested design parts, not speed or layout [OK]

Common Mistakes:

• Confusing coverage with simulation speed
• Thinking coverage generates synthesis reports
• Assuming coverage optimizes hardware layout

2. Which SystemVerilog construct is used to define a coverage point in code coverage?

easy

A. coverpoint

B. assertion

C. covergroup

D. property

Solution

1. Step 1: Recall coverage constructs

   SystemVerilog uses covergroup to group coverage points and coverpoint to define individual coverage points.

2. Step 2: Identify the coverage point

   The coverage point is specifically defined by coverpoint, inside a covergroup.

3. Final Answer:

   coverpoint -> Option A

4. Quick Check:

   Coverage point = coverpoint [OK]

Hint: Coverpoint defines coverage points inside covergroups [OK]

Common Mistakes:

• Confusing covergroup with coverpoint
• Using assertion or property for coverage points
• Mixing coverage with verification constructs

3. Given the following code snippet, what will be the coverage count for state after these values: 0, 1, 0, 2?

int state;
covergroup cg;
  coverpoint state;
endgroup

cg cg_inst = new();
state = 0;
cg_inst.sample();
state = 1;
cg_inst.sample();
state = 0;
cg_inst.sample();
state = 2;
cg_inst.sample();

medium

A. 1

B. 4

C. 2

D. 3

Solution

1. Step 1: Understand coverage counting

   Coverage counts unique values sampled by the coverpoint. Values 0,1,2 appear.

2. Step 2: Count unique values

   Values sampled: 0 (twice), 1, 2. Unique values are 0,1,2 -> 3 unique hits.

3. Final Answer:

   3 -> Option D

4. Quick Check:

   Unique states = 3 [OK]

Hint: Count unique sampled values for coverage count [OK]

Common Mistakes:

• Counting repeated samples multiple times
• Assuming total samples equal coverage count
• Ignoring unique value concept

4. Identify the error in this coverage code snippet:

int signal;
covergroup cg;
  coverpoint signal {
    bins low = {0};
    bins high = {1};
  }
endgroup

cg cg_inst = new();
signal = 2;
cg_inst.sample();

medium

A. Missing semicolon after coverpoint declaration

B. Bins do not cover the sampled value 2

C. covergroup must have a constructor

D. sample() method is not valid

Solution

1. Step 1: Analyze bins coverage

   Bins cover values 0 and 1 only. Sampled value is 2, which is not covered.

2. Step 2: Identify error impact

   Sampling 2 will not hit any bin, causing incomplete coverage.

3. Final Answer:

   Bins do not cover the sampled value 2 -> Option B

4. Quick Check:

   Bins coverage missing sampled value [OK]

Hint: Check if bins cover all sampled values [OK]

Common Mistakes:

• Ignoring uncovered sampled values
• Thinking semicolon is missing after coverpoint
• Assuming sample() method is invalid

5. How can you combine multiple coverpoints in a covergroup to track cross coverage of signals a and b in SystemVerilog?

hard

A. Define coverpoints for a and b and add a cross coverage for both inside the covergroup

B. Define separate covergroups for a and b without cross coverage

C. Use assertions to check a and b values

D. Sample a and b separately without grouping

Solution

1. Step 1: Understand covergroup composition

   A covergroup can contain multiple coverpoints to track individual signals.

2. Step 2: Use cross coverage

   Cross coverage tracks combinations of values from multiple coverpoints, here a and b.

3. Final Answer:

   Define coverpoints for a and b and add a cross coverage for both inside the covergroup -> Option A

4. Quick Check:

   Cross coverage = combined signal tracking [OK]

Hint: Use cross coverage inside covergroup for multiple signals [OK]

Common Mistakes:

• Not using cross coverage for combined signals
• Defining separate covergroups without cross
• Confusing assertions with coverage