Code coverage concepts in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a coverage variable for toggling a signal.

Verilog

covergroup cg_[1];
  option.per_instance = 1;
  coverpoint signal_toggle;
endgroup

Drag options to blanks, or click blank then click option'

Asignal_cov

Btoggle_cov

Ctoggle_point

Dsignal_group

Attempts:

3 left

💡 Hint

Common Mistakes

Using generic names that don't describe coverage purpose.

The coverage group name should be descriptive. toggle_cov clearly indicates coverage for toggling.

2fill in blank

medium

Complete the code to define a coverpoint for a 2-bit signal named 'state'.

Verilog

coverpoint [1] {
  bins idle = {2'b00};
  bins active = {2'b01, 2'b10};
  bins error = {2'b11};
}

Drag options to blanks, or click blank then click option'

Astate

Bstatus

Cmode

Dflag

Attempts:

3 left

💡 Hint

Common Mistakes

Using a different signal name that doesn't exist.

The coverpoint must match the signal name. Here, state is the correct signal.

3fill in blank

hard

Fix the error in the coverage bin definition for signal 'cmd' to cover values 0 to 3.

Verilog

coverpoint cmd {
  bins low_values = [1];
}

Drag options to blanks, or click blank then click option'

A[0:3]

B{0, 1, 2, 3}

C{0..3}

D(0, 1, 2, 3)

Attempts:

3 left

💡 Hint

Common Mistakes

Using curly braces with dots or commas incorrectly.

In SystemVerilog coverage bins, ranges are defined with square brackets like [0:3].

4fill in blank

hard

Fill both blanks to create a cross coverage between signals 'addr' and 'data'.

Verilog

cross [1], [2];

Drag options to blanks, or click blank then click option'

Aaddr

Bdata

Ccmd

Dflag

Attempts:

3 left

💡 Hint

Common Mistakes

Crossing unrelated signals or using the same signal twice.

Cross coverage is defined between two coverpoints. Here, addr and data are the signals to cross.

5fill in blank

hard

Fill all three blanks to define a covergroup with a coverpoint and a cross, then instantiate it.

Verilog

covergroup [1];
  coverpoint [2];
  cross [2], [3];
endgroup

[1] cg_inst = new();

Drag options to blanks, or click blank then click option'

Acg_example

Bsignal_a

Csignal_b

Dsignal_c

Attempts:

3 left

💡 Hint

Common Mistakes

Mismatching instance and covergroup names.

Using signals not declared.

The covergroup name is cg_example. The coverpoint and cross use signal_a and signal_b. Finally, the instance is created with the covergroup name.

Practice

1. What is the main purpose of code coverage in Verilog simulations?

easy

A. To generate synthesis reports

B. To speed up the simulation runtime

C. To check which parts of the design have been tested

D. To optimize the hardware layout

Solution

1. Step 1: Understand code coverage concept

   Code coverage tracks which parts of the Verilog design are exercised during simulation.

2. Step 2: Identify the main goal

   The goal is to ensure tests cover all design parts, improving test quality.

3. Final Answer:

   To check which parts of the design have been tested -> Option C

4. Quick Check:

   Code coverage = tested parts check [OK]

Hint: Code coverage shows tested design parts, not speed or layout [OK]

Common Mistakes:

• Confusing coverage with simulation speed
• Thinking coverage generates synthesis reports
• Assuming coverage optimizes hardware layout

2. Which SystemVerilog construct is used to define a coverage point in code coverage?

easy

A. coverpoint

B. assertion

C. covergroup

D. property

Solution

1. Step 1: Recall coverage constructs

   SystemVerilog uses covergroup to group coverage points and coverpoint to define individual coverage points.

2. Step 2: Identify the coverage point

   The coverage point is specifically defined by coverpoint, inside a covergroup.

3. Final Answer:

   coverpoint -> Option A

4. Quick Check:

   Coverage point = coverpoint [OK]

Hint: Coverpoint defines coverage points inside covergroups [OK]

Common Mistakes:

• Confusing covergroup with coverpoint
• Using assertion or property for coverage points
• Mixing coverage with verification constructs

3. Given the following code snippet, what will be the coverage count for state after these values: 0, 1, 0, 2?

int state;
covergroup cg;
  coverpoint state;
endgroup

cg cg_inst = new();
state = 0;
cg_inst.sample();
state = 1;
cg_inst.sample();
state = 0;
cg_inst.sample();
state = 2;
cg_inst.sample();

medium

A. 1

B. 4

C. 2

D. 3

Solution

1. Step 1: Understand coverage counting

   Coverage counts unique values sampled by the coverpoint. Values 0,1,2 appear.

2. Step 2: Count unique values

   Values sampled: 0 (twice), 1, 2. Unique values are 0,1,2 -> 3 unique hits.

3. Final Answer:

   3 -> Option D

4. Quick Check:

   Unique states = 3 [OK]

Hint: Count unique sampled values for coverage count [OK]

Common Mistakes:

• Counting repeated samples multiple times
• Assuming total samples equal coverage count
• Ignoring unique value concept

4. Identify the error in this coverage code snippet:

int signal;
covergroup cg;
  coverpoint signal {
    bins low = {0};
    bins high = {1};
  }
endgroup

cg cg_inst = new();
signal = 2;
cg_inst.sample();

medium

A. Missing semicolon after coverpoint declaration

B. Bins do not cover the sampled value 2

C. covergroup must have a constructor

D. sample() method is not valid

Solution

1. Step 1: Analyze bins coverage

   Bins cover values 0 and 1 only. Sampled value is 2, which is not covered.

2. Step 2: Identify error impact

   Sampling 2 will not hit any bin, causing incomplete coverage.

3. Final Answer:

   Bins do not cover the sampled value 2 -> Option B

4. Quick Check:

   Bins coverage missing sampled value [OK]

Hint: Check if bins cover all sampled values [OK]

Common Mistakes:

• Ignoring uncovered sampled values
• Thinking semicolon is missing after coverpoint
• Assuming sample() method is invalid

5. How can you combine multiple coverpoints in a covergroup to track cross coverage of signals a and b in SystemVerilog?

hard

A. Define coverpoints for a and b and add a cross coverage for both inside the covergroup

B. Define separate covergroups for a and b without cross coverage

C. Use assertions to check a and b values

D. Sample a and b separately without grouping

Solution

1. Step 1: Understand covergroup composition

   A covergroup can contain multiple coverpoints to track individual signals.

2. Step 2: Use cross coverage

   Cross coverage tracks combinations of values from multiple coverpoints, here a and b.

3. Final Answer:

   Define coverpoints for a and b and add a cross coverage for both inside the covergroup -> Option A

4. Quick Check:

   Cross coverage = combined signal tracking [OK]

Hint: Use cross coverage inside covergroup for multiple signals [OK]

Common Mistakes:

• Not using cross coverage for combined signals
• Defining separate covergroups without cross
• Confusing assertions with coverage