Why Simulation time control with #delay in Verilog? - Purpose & Use Cases

The Big Idea

What if you could tell your simulation exactly when to act, without messy code or mistakes?

The Scenario

Imagine you want to test a digital circuit by manually changing signals at exact times. You write many lines of code to set signals, wait, then set signals again, all by hand.

The Problem

This manual way is slow and confusing. You might forget to wait the right amount of time or mix up the order. It's easy to make mistakes and hard to fix them.

The Solution

Using #delay lets you tell the simulator to pause for a specific time before doing the next action. This makes your test code clear, simple, and easy to follow.

Before vs After

✗ Before

signal = 1; wait for 10 time units; signal = 0; wait for 5 time units;

✓ After

signal = 1; #10; signal = 0; #5;

What It Enables

You can precisely control when events happen in your simulation, making tests accurate and easy to write.

Real Life Example

Testing a flip-flop circuit by setting its input high, waiting exactly one clock cycle, then setting it low to see if the output changes correctly.

Key Takeaways

Manual timing is error-prone and hard to manage.

#delay pauses simulation cleanly and clearly.

It helps write accurate and readable test sequences.

Practice

1. What does the #delay statement do in Verilog simulation?

easy

A. Pauses the simulation for a specified time before executing the next statement

B. Immediately ends the simulation

C. Skips the next statement without delay

D. Changes the clock frequency during simulation

Solution

1. Step 1: Understand the role of #delay

   The #delay statement in Verilog is used to pause the simulation for a certain amount of time before the next statement runs.

2. Step 2: Compare options with the definition

   Only Pauses the simulation for a specified time before executing the next statement correctly describes this behavior. Options A, B, and C describe unrelated or incorrect actions.

3. Final Answer:

   Pauses the simulation for a specified time before executing the next statement -> Option A

4. Quick Check:

   #delay pauses simulation = D [OK]

Hint: Remember: #delay waits before next action runs [OK]

Common Mistakes:

• Thinking #delay ends simulation
• Confusing #delay with clock control
• Assuming #delay skips statements

2. Which of the following is the correct syntax to delay 10 time units in Verilog?

easy

A. #10 delay;

B. #delay 10;

C. delay #10;

D. #10;

Solution

1. Step 1: Recall correct delay syntax

   In Verilog, the correct syntax to delay is #time; where time is a number representing delay units.

2. Step 2: Match options to syntax

   #10; matches the correct syntax: #10;. Options A, C, and D are incorrect because they misuse keywords or add extra words.

3. Final Answer:

   #10; -> Option D

4. Quick Check:

   Delay syntax = #time; = B [OK]

Hint: Delay uses # followed directly by number and semicolon [OK]

Common Mistakes:

• Adding extra words after #delay
• Using #delay keyword instead of #number
• Missing semicolon after delay

3. What will be the output time sequence of the following Verilog code snippet?

initial begin
  $display("Time: %0t", $time);
  #5;
  $display("Time after delay: %0t", $time);
end

medium

A. Time: 0
Time after delay: 0

B. Time: 5
Time after delay: 10

C. Time: 0
Time after delay: 5

D. Time: 5
Time after delay: 5

Solution

1. Step 1: Understand initial time and delay effect

   The simulation starts at time 0. The first $display prints time 0. Then #5; delays simulation by 5 time units.

2. Step 2: Determine time after delay

   After the delay, the second $display prints the current time, which is 5.

3. Final Answer:

   Time: 0 Time after delay: 5 -> Option C

4. Quick Check:

   Initial time 0 + #5 delay = 5 [OK]

Hint: First print at 0, second after #5 delay at time 5 [OK]

Common Mistakes:

• Assuming time does not advance after #delay
• Printing time before delay as non-zero
• Confusing delay units with clock cycles

4. Identify the error in this Verilog code snippet using #delay:

initial begin
  #10
  $display("Delayed output");
end

medium

A. Incorrect use of $display

B. Missing semicolon after #10

C. Delay value must be in parentheses

D. initial block cannot have delays

Solution

1. Step 1: Check syntax of delay statement

   The delay statement #10 must be followed by a semicolon to separate it from the next statement.

2. Step 2: Verify other statements

   The $display statement is correct, delay values do not require parentheses, and initial blocks can have delays.

3. Final Answer:

   Missing semicolon after #10 -> Option B

4. Quick Check:

   Delay statements need semicolon = A [OK]

Hint: Always put semicolon after #delay number [OK]

Common Mistakes:

• Omitting semicolon after delay
• Adding parentheses around delay number
• Thinking delays not allowed in initial blocks

5. Given the following code, what will be the output times printed?

initial begin
  $display("Start time: %0t", $time);
  #3;
  $display("After first delay: %0t", $time);
  #2;
  $display("After second delay: %0t", $time);
end

Assuming timescale is 1ns / 1ps.

hard

A. Start time: 0
After first delay: 3
After second delay: 5

B. Start time: 0
After first delay: 2
After second delay: 4

C. Start time: 1
After first delay: 4
After second delay: 6

D. Start time: 0
After first delay: 5
After second delay: 7

Solution

1. Step 1: Analyze initial time and first delay

   The simulation starts at time 0. The first $display prints 0. Then #3; delays simulation by 3 time units, so time becomes 3.

2. Step 2: Analyze second delay and final time

   After printing time 3, the next #2; adds 2 more units, making time 5. The last $display prints 5.

3. Final Answer:

   Start time: 0 After first delay: 3 After second delay: 5 -> Option A

4. Quick Check:

   0 + 3 + 2 = 5 time units [OK]

Hint: Add delays cumulatively to get output times [OK]

Common Mistakes:

• Adding delays incorrectly or skipping first time 0
• Confusing timescale units
• Assuming delays reset time