Reg type and procedural assignment in Verilog

Introduction

We use reg type in Verilog to store values that can change inside a block of code. Procedural assignment lets us change these values step-by-step in a controlled way.

When you want to remember a value between steps in a process.

When you need to change a signal inside an <code>always</code> block.

When modeling simple memory or flip-flop behavior.

When you want to update a signal based on conditions or timing.

Syntax

Verilog

reg [width-1:0] name;
always @(sensitivity_list) begin
  name = value; // procedural assignment
end

reg means the variable can hold a value over time.

Procedural assignments happen inside always blocks.

Examples

Assigns 1 to a on every rising clock edge.

Verilog

reg a;
always @(posedge clk) begin
  a = 1'b1;
end

Increments a 4-bit counter on each clock pulse.

Verilog

reg [3:0] count;
always @(posedge clk) begin
  count = count + 1;
end

Sets flag based on input_signal changes.

Verilog

reg flag;
always @(*) begin
  if (input_signal) flag = 1'b0;
  else flag = 1'b1;
end

Sample Program

This module uses a reg type q that toggles its value on each clock pulse. If reset is high, q resets to 0.

Verilog

module simple_reg_example(input clk, input reset, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset) q = 1'b0;
    else q = ~q;
  end
endmodule

Important Notes

Use reg only inside procedural blocks like always.

Procedural assignments use = for blocking or <= for non-blocking assignments.

Remember, reg does not mean a hardware register always; it means a variable that holds value.

Summary

reg stores values that can change inside always blocks.

Procedural assignment updates reg variables step-by-step.

This helps model memory and sequential logic in hardware.

Practice

1. What is the main purpose of the reg type in Verilog?

easy

A. To store values inside procedural blocks like always.

B. To declare input ports for a module.

C. To define constant values that never change.

D. To represent wires that connect modules.

Solution

1. Step 1: Understand the role of reg

   reg is used to hold values that can change inside procedural blocks like always.

2. Step 2: Compare with other types

   Input ports and wires are not reg; constants are declared differently.

3. Final Answer:

   To store values inside procedural blocks like always. -> Option A

4. Quick Check:

   reg stores values in procedural blocks [OK]

Hint: Remember: reg holds values inside always blocks [OK]

Common Mistakes:

• Confusing reg with input or output ports
• Thinking reg is a constant
• Mixing reg with wire

2. Which of the following is the correct way to perform a blocking assignment to a reg inside an always block?

easy

A. reg_var = 1;

B. reg_var <= 1;

C. wire_var = 1;

D. reg_var := 1;

Solution

1. Step 1: Identify procedural assignment syntax

   Inside always blocks, = is used for blocking assignments to reg.

2. Step 2: Check each option

   reg_var = 1; is correct syntax for blocking; reg_var <= 1; is non-blocking; wire_var = 1; cannot assign to wire procedurally; reg_var := 1; is invalid in Verilog.

3. Final Answer:

   reg_var = 1; -> Option A

4. Quick Check:

   Procedural blocking assignment uses = for reg [OK]

Hint: Use = for blocking procedural reg assignments inside always [OK]

Common Mistakes:

• Using := which is not Verilog syntax
• Assigning to wire inside always
• Confusing blocking (=) and non-blocking (<=) without context

3. What will be the value of count after the following code executes once?

reg [3:0] count;
always @ (posedge clk) begin
  count = count + 1;
end

medium

A. count resets to 0

B. count remains unchanged

C. count increments by 1

D. Syntax error due to missing initial value

Solution

1. Step 1: Understand procedural increment

   On each positive clock edge, count is assigned its current value plus 1.

2. Step 2: Consider initial value

   If count was initialized or reset before, it increments by 1; no syntax error occurs without explicit initial value.

3. Final Answer:

   count increments by 1 -> Option C

4. Quick Check:

   Procedural assignment increments count [OK]

Hint: Procedural reg assignments update values on clock edges [OK]

Common Mistakes:

• Assuming count resets automatically
• Thinking missing initial value causes syntax error
• Confusing reg with wire behavior

4. Identify the error in this Verilog snippet:

reg flag;
always @ (posedge clk) begin
  flag = 1'b1;
end
assign flag = 1'b0;

medium

A. Missing semicolon after flag = 1'b1

B. Cannot assign flag both procedurally and continuously

C. Incorrect bit width for flag

D. No error, code is correct

Solution

1. Step 1: Check assignments to flag

   flag is assigned inside an always block and also by a continuous assign.

2. Step 2: Understand Verilog rules

   A reg cannot be driven by both procedural and continuous assignments simultaneously.

3. Final Answer:

   Cannot assign flag both procedurally and continuously -> Option B

4. Quick Check:

   Procedural and continuous assignments conflict [OK]

Hint: Avoid mixing procedural and continuous assignments on same reg [OK]

Common Mistakes:

• Ignoring conflict between procedural and continuous assignments
• Thinking missing semicolon causes error here
• Confusing reg and wire assignment rules

5. Given the following code, what will be the final value of state after two positive clock edges?

reg [1:0] state = 2'b00;
always @ (posedge clk) begin
  if (state == 2'b00)
    state = 2'b01;
  else
    state = 2'b10;
end

hard

A. state toggles between 2'b01 and 2'b10 infinitely

B. state = 2'b01

C. state = 2'b00

D. state = 2'b10

Solution

1. Step 1: Trace first clock edge

   Initial state is 2'b00, so after first clock edge it becomes 2'b01.

2. Step 2: Trace second clock edge

   Now state is 2'b01, so after second clock edge it becomes 2'b10.

3. Final Answer:

   state = 2'b10 -> Option D

4. Quick Check:

   State updates stepwise on clock edges [OK]

Hint: Follow state changes step-by-step on each clock edge [OK]

Common Mistakes:

• Assuming state stays at 2'b01 after two edges
• Thinking state resets to 2'b00 automatically
• Confusing procedural assignment timing