Array declaration in Verilog

Introduction

Arrays help you store many values in one place. This makes your code neat and easy to manage.

When you want to keep a list of signals or bits together.

When you need to handle multiple data items of the same type.

When you want to create memory blocks or registers.

When you want to loop through many values easily.

When you want to organize data for hardware operations.

Syntax

Verilog

reg [bit_width-1:0] array_name [0:array_size-1];

reg means the array stores values that can change.

The [bit_width-1:0] sets how many bits each element has.

The [0:array_size-1] sets how many elements are in the array.

Examples

This creates an array with 4 elements (0 to 3), each 8 bits wide.

Verilog

reg [7:0] data_array [0:3];

This creates an array of 2 elements, each 16 bits wide, using wire type.

Verilog

wire [15:0] address_bus [0:1];

This creates an array of 8 elements, each 1 bit wide.

Verilog

reg [0:0] single_bit_array [0:7];

This is an empty array (size zero). Usually avoided but shows edge case.

Verilog

reg [3:0] empty_array [0:-1];

Sample Program

This program creates an array of 4 bytes. It sets each byte to a value and prints them. You see how to declare, assign, and read array elements.

Verilog

module array_declaration_example();
  // Declare an array of 4 elements, each 8 bits wide
  reg [7:0] data_array [0:3];

  initial begin
    // Assign values to each element
    data_array[0] = 8'hAA; // 10101010
    data_array[1] = 8'h55; // 01010101
    data_array[2] = 8'hFF; // 11111111
    data_array[3] = 8'h00; // 00000000

    // Print all elements
    $display("Array elements:");
    $display("data_array[0] = %h", data_array[0]);
    $display("data_array[1] = %h", data_array[1]);
    $display("data_array[2] = %h", data_array[2]);
    $display("data_array[3] = %h", data_array[3]);
  end
endmodule

Important Notes

Array declaration time complexity is not applicable since it's a hardware description.

Arrays use space proportional to bit_width x array_size in hardware.

Common mistake: Mixing up bit width and array size syntax.

Use arrays when you need multiple similar signals grouped; use single registers for single values.

Summary

Arrays group many values of the same type in one variable.

Use reg [bit_width-1:0] array_name [0:size-1]; to declare.

Access elements by index like array_name[index].

Practice

1. What is the correct way to declare a 16-bit wide array with 8 elements in Verilog?

easy

A. reg [0:7] my_array [15:0];

B. reg my_array [15:0] [0:7];

C. reg [15:0] my_array [0:7];

D. reg [7:0] my_array [0:15];

Solution

1. Step 1: Understand bit width and size syntax

   In Verilog, the bit width is declared first as [bit_width-1:0], so for 16 bits it is [15:0].

2. Step 2: Declare array size correctly

   The array size is declared after the variable name as [0:size-1], so for 8 elements it is [0:7].

3. Final Answer:

   reg [15:0] my_array [0:7]; -> Option C

4. Quick Check:

   Bit width then array size = reg [15:0] my_array [0:7]; [OK]

Hint: Bit width first, then array size in brackets [OK]

Common Mistakes:

• Swapping bit width and array size positions
• Using incorrect bit range like [0:7] for bit width
• Confusing array size with bit width

2. Which of the following is a syntax error when declaring an array in Verilog?

easy

A. reg [7:0] data_array [0:15];

B. reg [7:0] data_array [0:7];

C. reg [0:7] data_array [0:15];

D. reg [7:0] data_array [15:0];

Solution

1. Step 1: Check array size declaration

   Array size must be declared as [start_index:end_index] with start_index less than end_index, usually [0:size-1].

2. Step 2: Identify invalid range

   reg [7:0] data_array [15:0]; uses [15:0], which is reversed and invalid for array indexing.

3. Final Answer:

   reg [7:0] data_array [15:0]; -> Option D

4. Quick Check:

   Array index must be ascending range [OK]

Hint: Array index must go from low to high [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width range with array index range
• Forgetting semicolon at end

3. Given the declaration reg [3:0] arr [0:3]; and the assignments arr[0] = 4'b1010;, arr[1] = 4'b0101;, what is the value of arr[1]?

medium

A. 4'b0101

B. 4'b1111

C. 4'b1010

D. 4'b0000

Solution

1. Step 1: Understand array declaration and assignments

   The array arr has 4 elements indexed 0 to 3, each 4 bits wide. arr[0] is assigned 1010, arr[1] is assigned 0101.

2. Step 2: Identify value of arr[1]

   arr[1] was explicitly assigned 4'b0101, so its value is 0101.

3. Final Answer:

   4'b0101 -> Option A

4. Quick Check:

   arr[1] = 4'b0101 [OK]

Hint: Index matches assigned value directly [OK]

Common Mistakes:

• Mixing up indices and values
• Assuming default zero without assignment
• Confusing bit width with array size

4. Identify the error in the following Verilog array declaration:

reg [7:0] mem_array [7:0];

medium

A. Array size range should be [0:7], not [7:0]

B. Bit width and array size are swapped

C. No error, declaration is correct

D. Missing semicolon at the end

Solution

1. Step 1: Analyze array size range

   The array size is declared as [7:0], which is a descending range and invalid for array indexing.

2. Step 2: Correct array size range

   The correct array size should be ascending, [0:7], to declare 8 elements indexed 0 to 7.

3. Final Answer:

   Array size range should be [0:7], not [7:0] -> Option A

4. Quick Check:

   Array index must be ascending [OK]

Hint: Array index must count up, not down [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width with array size
• Assuming [7:0] is valid for arrays

5. How would you declare a 2-dimensional array in Verilog with 4 rows and 8 columns, each element 8 bits wide?

hard

A. reg [7:0] matrix [0:7][0:3];

B. reg [7:0] matrix [0:3][0:7];

C. reg matrix [7:0][3:0];

D. reg [3:0] matrix [7:0];

Solution

1. Step 1: Understand 2D array declaration syntax

   In Verilog, multi-dimensional arrays are declared by stacking sizes after the variable name. The first dimension is rows, second is columns.

2. Step 2: Apply correct sizes and bit width

   Each element is 8 bits wide, so bit width is [7:0]. Rows are 4 elements indexed 0 to 3, columns are 8 elements indexed 0 to 7.

3. Final Answer:

   reg [7:0] matrix [0:3][0:7]; -> Option B

4. Quick Check:

   Bit width then rows then columns [OK]

Hint: Declare bit width first, then each dimension [OK]

Common Mistakes:

• Swapping row and column indices
• Incorrect bit width declaration
• Using reversed index ranges