Port declaration (input, output, inout) in Verilog

Introduction

Ports let you connect your Verilog module to the outside world. They define how signals come in, go out, or both.

When you want to send data into a module from another module or testbench.

When you want to send data out from a module to other parts of your design.

When a signal needs to both enter and leave a module (bidirectional).

When designing hardware blocks that communicate with each other.

When creating reusable modules with clear input and output connections.

Syntax

Verilog

module module_name (
    input wire input_name,
    output wire output_name,
    inout wire bidir_name
);

input means the signal goes into the module.

output means the signal comes out of the module.

inout means the signal can go both ways (bidirectional).

Examples

This module has an input clock signal and an output LED signal.

Verilog

module simple_module (
    input wire clk,
    output wire led
);

This module has a bidirectional data line that can send and receive data.

Verilog

module bidir_example (
    inout wire data_line
);

This module uses all three port types: input, output, and inout.

Verilog

module mixed_ports (
    input wire reset,
    output wire done,
    inout wire bus
);

Sample Program

This module takes two inputs a and b, outputs their XOR as sum, and has a bidirectional data_line which is driven low.

Verilog

module port_example (
    input wire a,
    input wire b,
    output wire sum,
    inout wire data_line
);

    assign sum = a ^ b; // sum is XOR of inputs

    // data_line is bidirectional, here just driven low
    assign data_line = 1'b0;

endmodule

Important Notes

Use wire type for ports unless you need to store values inside the module (then use reg internally).

Bidirectional ports (inout) are often used for data buses or shared lines.

Always clearly define port directions to avoid confusion and errors in hardware design.

Summary

Ports connect your module to other parts of your design.

input brings signals into the module.

output sends signals out of the module.

inout allows signals to go both ways.

Practice

1. Which keyword in Verilog is used to declare a port that receives signals from outside the module?

easy

A. input

B. output

C. inout

D. wire

Solution

1. Step 1: Understand port directions

   In Verilog, ports can be inputs, outputs, or bidirectional (inout).

2. Step 2: Identify the keyword for receiving signals

   The keyword input is used to declare ports that receive signals from outside the module.

3. Final Answer:

   input -> Option A

4. Quick Check:

   input = receives signals [OK]

Hint: Input ports receive signals from outside [OK]

Common Mistakes:

• Confusing output with input
• Using wire instead of input for ports
• Thinking inout means input only

2. Which of the following is the correct way to declare a 4-bit output port named data_out in Verilog?

easy

A. inout [4:0] data_out;

B. input [3:0] data_out;

C. output [3:0] data_out;

D. output data_out[3:0];

Solution

1. Step 1: Check port direction and width syntax

   Output ports use the keyword output. The width is declared as [3:0] for 4 bits.

2. Step 2: Validate the syntax correctness

   output [3:0] data_out; correctly declares a 4-bit output port as output [3:0] data_out;. output data_out[3:0]; has incorrect syntax placing the width after the name.

3. Final Answer:

   output [3:0] data_out; -> Option C

4. Quick Check:

   output [3:0] name; is correct syntax [OK]

Hint: Declare width before port name with brackets [OK]

Common Mistakes:

• Placing width after port name
• Using input instead of output
• Incorrect bit range like [4:0]

3. Consider this Verilog module header:

module example(input clk, output reg ready, inout wire data);
// module body
endmodule

Which statement about the ports is true?

medium

A. clk is an input port, ready is an output port, data is a bidirectional port

B. clk is an output port, ready is an input port, data is an output port

C. clk is a bidirectional port, ready is an input port, data is an output port

D. All ports are inputs by default

Solution

1. Step 1: Identify each port direction from declaration

   input clk means clk is input, output reg ready means ready is output, and inout wire data means data is bidirectional.

2. Step 2: Match each port with its direction

   clk is an input port, ready is an output port, data is a bidirectional port correctly matches clk as input, ready as output, and data as inout (bidirectional).

3. Final Answer:

   clk is input, ready is output, data is bidirectional -> Option A

4. Quick Check:

   input, output, inout match ports [OK]

Hint: Match keywords input/output/inout to port roles [OK]

Common Mistakes:

• Mixing input and output roles
• Assuming all ports default to input
• Ignoring reg or wire keywords

4. Identify the error in this Verilog port declaration:

module test_module(clk, data_out, inout_signal);
  input wire clk;
  output data_out;
  inout inout_signal
endmodule

medium

A. inout keyword is invalid in port list

B. input wire cannot be used for clk

C. output port must be declared as reg

D. Missing semicolon after inout_signal declaration

Solution

1. Step 1: Check syntax of port declarations

   In this non-ANSI style Verilog module, port names are listed in the header, and directions/types are declared inside the module body. Each declaration must end with a semicolon.

2. Step 2: Identify the specific error

   The declaration inout inout_signal lacks the required semicolon.

3. Final Answer:

   Missing semicolon after inout_signal declaration -> Option D

4. Quick Check:

   Declarations inside module end with semicolon [OK]

Hint: Port declarations inside module end with semicolon [OK]

Common Mistakes:

• Missing semicolons after port declarations
• Thinking output must be reg always
• Believing inout is invalid keyword

5. You want to design a Verilog module with a bidirectional data bus named bus that is 8 bits wide. Which is the correct port declaration and internal signal type to allow reading and writing on bus?

hard

A. input [7:0] bus; reg [7:0] bus_internal;

B. inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz;

C. output [7:0] bus; wire [7:0] bus_internal;

D. inout [7:0] bus; wire bus_internal; assign bus = write_enable ? data_out : 8'bz;

Solution

1. Step 1: Understand bidirectional port requirements

   Bidirectional ports use inout and require internal signals to store data for output, typically declared as reg for driven values.

2. Step 2: Analyze each option for correctness

   inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz; correctly declares inout [7:0] bus and uses reg [7:0] bus_internal for internal storage, with an assignment controlling bus output with high impedance when not writing.

3. Final Answer:

   inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz; -> Option B

4. Quick Check:

   inout with reg internal and tri-state assign [OK]

Hint: Use inout with reg and tri-state assign for bidirectional bus [OK]

Common Mistakes:

• Using wire instead of reg for internal signal
• Declaring bus as input or output only
• Not using tri-state (8'bz) for bus when not driving