Simulation time control with #delay in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog code with #delay?

Consider the following Verilog code snippet. What will be the order and timing of the printed messages?

Verilog

module test;
  initial begin
    $display("Start at time %0t", $time);
    #5 $display("After 5 time units at %0t", $time);
    #3 $display("After 8 time units at %0t", $time);
  end
endmodule

A

Start at time 0
After 5 time units at 8
After 8 time units at 11

B

Start at time 0
After 5 time units at 5
After 8 time units at 3

C

Start at time 0
After 5 time units at 5
After 8 time units at 8

D

Start at time 0
After 5 time units at 0
After 8 time units at 3

💡 Hint

Remember that delays accumulate in sequence inside an initial block.

The first $display runs at time 0. Then #5 delays 5 units, so the second $display runs at time 5. Then #3 delays 3 more units, so the third $display runs at time 8.

❓ Predict Output

intermediate

What is the value of 'count' after this Verilog code runs?

Analyze the following Verilog code. What is the final value of count after the initial block completes?

Verilog

module test;
  integer count = 0;
  initial begin
    count = 1;
    #10 count = count + 1;
    #5 count = count + 2;
  end
endmodule

A 4

B 1

C 3

D 0

💡 Hint

Delays add up and assignments happen after each delay.

Initially count=0, then set to 1 immediately. After 10 time units, count=2. After 5 more time units (total 15), count=4.

🔧 Debug

advanced

Which option causes a simulation time error or unexpected behavior?

Given these Verilog snippets using #delay, which one will cause a simulation time to not advance as expected or cause a runtime issue?

A initial begin #0 $display("Time: %0t", $time); end

B initial begin #10 $display("Time: %0t", $time); end

C initial begin #5 $display("Time: %0t", $time); end

D initial begin #(-5) $display("Time: %0t", $time); end

💡 Hint

Check if negative delays are allowed in Verilog simulation.

Negative delays like #(-5) are illegal and cause simulation errors. Zero or positive delays are valid.

🧠 Conceptual

advanced

How does #delay affect concurrent initial blocks in Verilog?

Consider two initial blocks running concurrently with different #delays. Which statement is true about their execution?

A Delays in one initial block pause all other initial blocks.

B Each initial block runs independently and delays only affect that block's timing.

C Delays cause the entire simulation to freeze until all delays complete.

D Delays synchronize all initial blocks to run at the same time.

💡 Hint

Think about concurrency and how delays work per process.

Each initial block is a separate process. Delays only pause that process, not others.

❓ Predict Output

expert

What is the output order and timing of this Verilog code with nested delays?

Analyze the following Verilog code. What will be printed and at what simulation times?

Verilog

module test;
  initial begin
    $display("Start at %0t", $time);
    fork
      begin
        #3 $display("Fork 1 at %0t", $time);
        #2 $display("Fork 1 later at %0t", $time);
      end
      begin
        #1 $display("Fork 2 at %0t", $time);
        #4 $display("Fork 2 later at %0t", $time);
      end
    join
    $display("End at %0t", $time);
  end
endmodule

A

Start at 0
Fork 2 at 1
Fork 1 at 3
Fork 1 later at 5
Fork 2 later at 5
End at 5

B

Start at 0
Fork 1 at 3
Fork 2 at 1
Fork 1 later at 5
Fork 2 later at 5
End at 5

C

Start at 0
Fork 2 at 1
Fork 1 at 3
Fork 1 later at 5
Fork 2 later at 5
End at 6

D

Start at 0
Fork 1 at 3
Fork 2 at 1
Fork 1 later at 5
Fork 2 later at 5
End at 6

💡 Hint

Remember fork-join waits for all forked blocks to finish before continuing.

Start prints at 0. Fork 2 prints at 1, Fork 1 at 3. Then Fork 1 later and Fork 2 later both print at 5. join waits until time 5. End prints at 5.

Practice

1. What does the #delay statement do in Verilog simulation?

easy

A. Pauses the simulation for a specified time before executing the next statement

B. Immediately ends the simulation

C. Skips the next statement without delay

D. Changes the clock frequency during simulation

Solution

1. Step 1: Understand the role of #delay

   The #delay statement in Verilog is used to pause the simulation for a certain amount of time before the next statement runs.

2. Step 2: Compare options with the definition

   Only Pauses the simulation for a specified time before executing the next statement correctly describes this behavior. Options A, B, and C describe unrelated or incorrect actions.

3. Final Answer:

   Pauses the simulation for a specified time before executing the next statement -> Option A

4. Quick Check:

   #delay pauses simulation = D [OK]

Hint: Remember: #delay waits before next action runs [OK]

Common Mistakes:

• Thinking #delay ends simulation
• Confusing #delay with clock control
• Assuming #delay skips statements

2. Which of the following is the correct syntax to delay 10 time units in Verilog?

easy

A. #10 delay;

B. #delay 10;

C. delay #10;

D. #10;

Solution

1. Step 1: Recall correct delay syntax

   In Verilog, the correct syntax to delay is #time; where time is a number representing delay units.

2. Step 2: Match options to syntax

   #10; matches the correct syntax: #10;. Options A, C, and D are incorrect because they misuse keywords or add extra words.

3. Final Answer:

   #10; -> Option D

4. Quick Check:

   Delay syntax = #time; = B [OK]

Hint: Delay uses # followed directly by number and semicolon [OK]

Common Mistakes:

• Adding extra words after #delay
• Using #delay keyword instead of #number
• Missing semicolon after delay

3. What will be the output time sequence of the following Verilog code snippet?

initial begin
  $display("Time: %0t", $time);
  #5;
  $display("Time after delay: %0t", $time);
end

medium

A. Time: 0
Time after delay: 0

B. Time: 5
Time after delay: 10

C. Time: 0
Time after delay: 5

D. Time: 5
Time after delay: 5

Solution

1. Step 1: Understand initial time and delay effect

   The simulation starts at time 0. The first $display prints time 0. Then #5; delays simulation by 5 time units.

2. Step 2: Determine time after delay

   After the delay, the second $display prints the current time, which is 5.

3. Final Answer:

   Time: 0 Time after delay: 5 -> Option C

4. Quick Check:

   Initial time 0 + #5 delay = 5 [OK]

Hint: First print at 0, second after #5 delay at time 5 [OK]

Common Mistakes:

• Assuming time does not advance after #delay
• Printing time before delay as non-zero
• Confusing delay units with clock cycles

4. Identify the error in this Verilog code snippet using #delay:

initial begin
  #10
  $display("Delayed output");
end

medium

A. Incorrect use of $display

B. Missing semicolon after #10

C. Delay value must be in parentheses

D. initial block cannot have delays

Solution

1. Step 1: Check syntax of delay statement

   The delay statement #10 must be followed by a semicolon to separate it from the next statement.

2. Step 2: Verify other statements

   The $display statement is correct, delay values do not require parentheses, and initial blocks can have delays.

3. Final Answer:

   Missing semicolon after #10 -> Option B

4. Quick Check:

   Delay statements need semicolon = A [OK]

Hint: Always put semicolon after #delay number [OK]

Common Mistakes:

• Omitting semicolon after delay
• Adding parentheses around delay number
• Thinking delays not allowed in initial blocks

5. Given the following code, what will be the output times printed?

initial begin
  $display("Start time: %0t", $time);
  #3;
  $display("After first delay: %0t", $time);
  #2;
  $display("After second delay: %0t", $time);
end

Assuming timescale is 1ns / 1ps.

hard

A. Start time: 0
After first delay: 3
After second delay: 5

B. Start time: 0
After first delay: 2
After second delay: 4

C. Start time: 1
After first delay: 4
After second delay: 6

D. Start time: 0
After first delay: 5
After second delay: 7

Solution

1. Step 1: Analyze initial time and first delay

   The simulation starts at time 0. The first $display prints 0. Then #3; delays simulation by 3 time units, so time becomes 3.

2. Step 2: Analyze second delay and final time

   After printing time 3, the next #2; adds 2 more units, making time 5. The last $display prints 5.

3. Final Answer:

   Start time: 0 After first delay: 3 After second delay: 5 -> Option A

4. Quick Check:

   0 + 3 + 2 = 5 time units [OK]

Hint: Add delays cumulatively to get output times [OK]

Common Mistakes:

• Adding delays incorrectly or skipping first time 0
• Confusing timescale units
• Assuming delays reset time