Conditional (ternary) operator in Verilog

Introduction

The conditional (ternary) operator lets you choose between two values based on a condition in a simple way.

When you want to assign a value based on a condition without writing a full if-else block.

When you need to select between two signals in hardware design.

When you want to write compact code for simple decisions.

When you want to set default values depending on a flag.

When you want to make your code easier to read by avoiding multiple lines.

Syntax

Verilog

condition ? value_if_true : value_if_false;

The condition is evaluated first.

If condition is true (non-zero), the expression returns value_if_true, otherwise value_if_false.

Examples

Selects a if sel is 1, otherwise selects b.

Verilog

assign out = (sel == 1) ? a : b;

Assigns the greater of x or y to result.

Verilog

wire [3:0] result = (x > y) ? x : y;

Turns on led if button_pressed is true, else turns it off.

Verilog

assign led = (button_pressed) ? 1'b1 : 1'b0;

Sample Program

This example shows a simple module using the ternary operator to select between inputs a and b based on sel. The testbench prints the output for different input combinations.

Verilog

module ternary_example(input wire sel, input wire a, input wire b, output wire out);
  assign out = sel ? a : b;
endmodule

// Testbench
module test;
  reg sel, a, b;
  wire out;
  ternary_example uut(sel, a, b, out);

  initial begin
    $display("sel a b | out");
    sel = 0; a = 0; b = 0; #1 $display("%b   %b %b | %b", sel, a, b, out);
    sel = 0; a = 0; b = 1; #1 $display("%b   %b %b | %b", sel, a, b, out);
    sel = 1; a = 1; b = 0; #1 $display("%b   %b %b | %b", sel, a, b, out);
    sel = 1; a = 0; b = 1; #1 $display("%b   %b %b | %b", sel, a, b, out);
    $finish;
  end
endmodule

Important Notes

The ternary operator is a compact way to write simple if-else assignments.

It is often used in assign statements for combinational logic.

For complex conditions or multiple choices, use nested ternary operators carefully or switch to if-else blocks for clarity.

Summary

The conditional (ternary) operator chooses between two values based on a condition.

It helps write shorter and clearer code for simple decisions.

Use it in assign statements to create combinational logic easily.

Practice

1. What does the conditional (ternary) operator condition ? value_if_true : value_if_false do in Verilog?

easy

A. It repeats a block of code multiple times.

B. It selects one of two values based on the condition's truth.

C. It declares a new variable.

D. It comments out a line of code.

Solution

1. Step 1: Understand the operator's purpose

   The conditional operator evaluates a condition and chooses between two values.

2. Step 2: Recognize the syntax meaning

   If the condition is true, it returns the first value; otherwise, it returns the second value.

3. Final Answer:

   It selects one of two values based on the condition's truth. -> Option B

4. Quick Check:

   Conditional operator chooses value based on condition [OK]

Hint: Remember: condition ? true_value : false_value picks one value [OK]

Common Mistakes:

• Thinking it repeats code like a loop
• Confusing it with variable declaration
• Assuming it comments code

2. Which of the following is the correct syntax for using the conditional (ternary) operator in Verilog?

easy

A. assign out = ? a : b;

B. assign out = a > b ? a, b;

C. assign out = a > b ? a : ;

D. assign out = (a > b) ? a : b;

Solution

1. Step 1: Check the syntax format

   The correct syntax is: condition ? value_if_true : value_if_false;

2. Step 2: Verify each option

   assign out = (a > b) ? a : b; matches the correct syntax with parentheses and colon separating values.

3. Final Answer:

   assign out = (a > b) ? a : b; -> Option D

4. Quick Check:

   Correct ternary syntax uses ? and : properly [OK]

Hint: Look for ? and : with condition before ? [OK]

Common Mistakes:

• Using comma instead of colon
• Missing value after colon
• Starting with ? without condition

3. What is the output value of out after this Verilog code runs?

wire [3:0] a = 4'd7;
wire [3:0] b = 4'd10;
wire [3:0] out;
assign out = (a > b) ? a : b;

medium

A. 10

B. 7

C. 0

D. Syntax error

Solution

1. Step 1: Evaluate the condition (a > b)

   a is 7, b is 10, so 7 > 10 is false.

2. Step 2: Choose value based on condition

   Since condition is false, out gets value b, which is 10.

3. Final Answer:

   10 -> Option A

4. Quick Check:

   7 > 10 is false, so out = b = 10 [OK]

Hint: Check condition result true or false to pick value [OK]

Common Mistakes:

• Assuming a is greater than b
• Confusing true and false branches
• Thinking code has syntax error

4. Identify the error in this Verilog code using the conditional operator:

assign result = (x == 1) ? 5 : ;

medium

A. Condition should use single equals (=)

B. Incorrect use of parentheses

C. Missing value after colon (:)

D. No error, code is correct

Solution

1. Step 1: Check the ternary operator structure

   The operator needs a value after the colon to use if condition is false.

2. Step 2: Identify missing part

   Here, after colon (:), no value is given, causing syntax error.

3. Final Answer:

   Missing value after colon (:) -> Option C

4. Quick Check:

   Conditional operator needs both true and false values [OK]

Hint: Always provide both true and false values after ? and : [OK]

Common Mistakes:

• Leaving false value empty
• Using == incorrectly (it's correct here)
• Ignoring missing value error

5. Given this Verilog snippet, what is the value of final_out?

wire [3:0] a = 4'd3;
wire [3:0] b = 4'd7;
wire [3:0] c = 4'd5;
wire [3:0] final_out;
assign final_out = (a > b) ? ((b > c) ? b : c) : ((a > c) ? a : c);

hard

A. 5

B. 7

C. 3

D. Syntax error

Solution

1. Step 1: Evaluate outer condition (a > b)

   a=3, b=7, so 3 > 7 is false, go to false branch.

2. Step 2: Evaluate inner condition in false branch (a > c)

   a=3, c=5, so 3 > 5 is false, select c which is 5.

3. Final Answer:

   5 -> Option A

4. Quick Check:

   Nested ternary picks c=5 as final_out [OK]

Hint: Evaluate nested conditions step-by-step from outside in [OK]

Common Mistakes:

• Mixing true and false branches
• Ignoring nested ternary structure
• Assuming syntax error without checking