Module as the basic building block in Verilog

Introduction

A module is like a small machine that does a specific job in a digital circuit. It helps organize and build bigger circuits by connecting these small machines together.

When you want to design a simple part of a circuit, like a gate or a counter.

When you want to reuse the same circuit design in different places.

When you want to break a big circuit into smaller, easier parts.

When you want to test a small part of your design separately.

When you want to share your design with others in a clear way.

Syntax

Verilog

module module_name (port_list);
  // declarations
  // statements
endmodule

The module keyword starts the module definition.

The endmodule keyword ends the module.

Examples

This module defines a simple AND gate with two inputs and one output.

Verilog

module and_gate (input a, input b, output y);
  assign y = a & b;
endmodule

This module defines an inverter that flips the input signal.

Verilog

module inverter (input in, output out);
  assign out = ~in;
endmodule

This module defines a 4-bit counter that increases on each clock pulse and resets when reset is high.

Verilog

module simple_counter (input clk, input reset, output reg [3:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 0;
    else
      count <= count + 1;
  end
endmodule

Sample Program

This program defines an AND gate module and a testbench to check its output for all input combinations. The testbench changes inputs every 10 time units and prints the result.

Verilog

module and_gate (input a, input b, output y);
  assign y = a & b;
endmodule

module testbench;
  reg a, b;
  wire y;

  and_gate uut (.a(a), .b(b), .y(y));

  initial begin
    a = 0; b = 0;
    #10 a = 0; b = 1;
    #10 a = 1; b = 0;
    #10 a = 1; b = 1;
    #10 $finish;
  end

  initial begin
    $monitor("At time %0t: a=%b b=%b y=%b", $time, a, b, y);
  end
endmodule

Important Notes

Modules can have inputs, outputs, and internal signals.

Use meaningful names for modules and ports to keep your design clear.

You can connect modules together to build complex circuits.

Summary

A module is the basic building block in Verilog to create parts of a digital circuit.

Modules help organize, reuse, and test your designs easily.

Every module starts with module and ends with endmodule.

Practice

1.

What is the main purpose of a module in Verilog?

easy

A. It defines a reusable block of hardware design.

B. It runs software programs inside the chip.

C. It stores data permanently like a hard drive.

D. It controls the power supply of the circuit.

Solution

1. Step 1: Understand what a module represents

   A module in Verilog is a block that describes hardware behavior or structure.

2. Step 2: Identify the purpose of modules

   Modules help organize and reuse hardware design parts, not software or power control.

3. Final Answer:

   It defines a reusable block of hardware design. -> Option A

4. Quick Check:

   Module = reusable hardware block [OK]

Hint: Modules are like building blocks for hardware [OK]

Common Mistakes:

• Thinking modules run software code
• Confusing modules with memory storage
• Assuming modules control power

2.

Which of the following is the correct way to start and end a Verilog module named my_module?

?

easy

A. start my_module; finish

B. module my_module(); endmodule

C. begin my_module() end

D. module: my_module() endmodule:

Solution

1. Step 1: Recall Verilog module syntax

   A module starts with the keyword module followed by the module name and ends with endmodule.

2. Step 2: Check each option

   module my_module(); endmodule uses correct keywords and syntax. Others use invalid keywords or punctuation.

3. Final Answer:

   module my_module(); endmodule -> Option B

4. Quick Check:

   module ... endmodule = correct syntax [OK]

Hint: Modules always start with 'module' and end with 'endmodule' [OK]

Common Mistakes:

• Using wrong keywords like start or finish
• Missing parentheses after module name
• Adding colons or semicolons incorrectly

3.

What will be the output of the following Verilog module when input_a = 1 and input_b = 0?

module simple_and(input input_a, input input_b, output reg out);
  always @(*) begin
    out = input_a & input_b;
  end
endmodule

medium

A. out = input_b

B. out = 1

C. out = input_a

D. out = 0

Solution

1. Step 1: Understand the operation inside the module

   The module assigns out as the AND of input_a and input_b.

2. Step 2: Calculate the AND of inputs

   Given input_a = 1 and input_b = 0, 1 & 0 = 0.

3. Final Answer:

   out = 0 -> Option D

4. Quick Check:

   1 AND 0 = 0 [OK]

Hint: AND output is 1 only if both inputs are 1 [OK]

Common Mistakes:

• Assuming output equals one input directly
• Confusing AND with OR operation
• Ignoring that output is reg type

4.

Identify the error in this Verilog module code:

module faulty_module(input a, input b, output reg c);
  always @(*) begin
    c = a | b
  end
endmodule

medium

A. Wrong sensitivity list in always block.

B. Incorrect use of 'reg' for output.

C. Missing semicolon after assignment inside always block.

D. Module name should be capitalized.

Solution

1. Step 1: Check syntax inside always block

   The assignment c = a | b is missing a semicolon at the end.

2. Step 2: Verify other parts

   Using reg for output is correct; sensitivity list @(*) is valid; module names can be lowercase.

3. Final Answer:

   Missing semicolon after assignment inside always block. -> Option C

4. Quick Check:

   Statements inside always need semicolons [OK]

Hint: Always end statements inside always block with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after assignment
• Thinking output cannot be reg
• Believing sensitivity list must list signals explicitly

5.

You want to create a Verilog module named counter that counts from 0 to 3 repeatedly using a 2-bit output count. Which module header and port declaration is correct?

hard

A. module counter(input clk, output reg [1:0] count); endmodule

B. module counter(output reg [2:0] count, input clk); endmodule

C. module counter(input clk, output [1:0] count); endmodule

D. module counter(input clk, output reg count[1:0]); endmodule

Solution

1. Step 1: Identify correct port order and types

   The clock input clk should be input, and count is a 2-bit register output, declared as output reg [1:0] count.

2. Step 2: Check each option

   module counter(input clk, output reg [1:0] count); endmodule correctly declares ports and types. module counter(output reg [2:0] count, input clk); endmodule has wrong bit width. module counter(input clk, output [1:0] count); endmodule misses reg for output assigned inside always block. module counter(input clk, output reg count[1:0]); endmodule uses incorrect syntax for bus declaration.

3. Final Answer:

   module counter(input clk, output reg [1:0] count); endmodule -> Option A

4. Quick Check:

   Output reg [1:0] count with input clk = correct [OK]

Hint: Use 'output reg [bits]' for outputs assigned in always blocks [OK]

Common Mistakes:

• Forgetting 'reg' for output assigned in always block
• Incorrect bus declaration syntax
• Swapping input and output order