Simulation time control with #delay in Verilog - Mini Project: Build & Apply

Simulation Time Control with #delay in Verilog

📖 Scenario: You are learning how to control the timing of events in a digital circuit simulation using Verilog. Timing control is important to see how signals change over time.

🎯 Goal: Build a simple Verilog testbench that uses #delay statements to change a signal value at specific simulation times and observe the output.

📋 What You'll Learn

Create a signal variable called clk and initialize it to 0

Create a delay variable called half_period and set it to 5

Use a forever loop with #delay to toggle clk every half_period

Print the value of clk at each toggle using $display

💡 Why This Matters

🌍 Real World

Timing control with delays is essential in digital circuit simulation to test how signals behave over time before hardware is built.

💼 Career

Understanding simulation time control helps hardware engineers verify designs and catch errors early, saving time and cost in chip development.

1

Create the clock signal variable

Create a reg variable called clk and set it to 0 inside an initial block.

Verilog

initial begin
    // Your code here
end

Hint

Use reg clk; to declare the clock signal. Inside initial begin ... end, set clk = 0;.

2

Create the delay variable

Add an integer variable called half_period and set it to 5 inside the initial block.

Verilog

module testbench;
    reg clk;
    initial begin
        clk = 0;
        // Your code here
    end
endmodule

Hint

Declare integer half_period; before the initial block or inside it. Then assign half_period = 5;.

3

Toggle the clock signal using #delay

Inside the initial block, add a forever loop that waits for #half_period and then toggles clk by assigning clk = ~clk;.

Verilog

module testbench;
    reg clk;
    integer half_period;
    initial begin
        clk = 0;
        half_period = 5;
        // Your code here
    end
endmodule

Hint

Use forever begin ... end to create an infinite loop. Inside it, write #half_period clk = ~clk; to wait and toggle.

4

Display the clock value at each toggle

Add a $display statement inside the forever loop to print the current simulation time and the value of clk using $time and clk.

Verilog

module testbench;
    reg clk;
    integer half_period;
    initial begin
        clk = 0;
        half_period = 5;
        forever begin
            #half_period clk = ~clk;
            // Your code here
        end
    end
endmodule

Hint

Use $display("At time %0t, clk = %b", $time, clk); to print time and clock value.

Practice

1. What does the #delay statement do in Verilog simulation?

easy

A. Pauses the simulation for a specified time before executing the next statement

B. Immediately ends the simulation

C. Skips the next statement without delay

D. Changes the clock frequency during simulation

Solution

1. Step 1: Understand the role of #delay

   The #delay statement in Verilog is used to pause the simulation for a certain amount of time before the next statement runs.

2. Step 2: Compare options with the definition

   Only Pauses the simulation for a specified time before executing the next statement correctly describes this behavior. Options A, B, and C describe unrelated or incorrect actions.

3. Final Answer:

   Pauses the simulation for a specified time before executing the next statement -> Option A

4. Quick Check:

   #delay pauses simulation = D [OK]

Hint: Remember: #delay waits before next action runs [OK]

Common Mistakes:

• Thinking #delay ends simulation
• Confusing #delay with clock control
• Assuming #delay skips statements

2. Which of the following is the correct syntax to delay 10 time units in Verilog?

easy

A. #10 delay;

B. #delay 10;

C. delay #10;

D. #10;

Solution

1. Step 1: Recall correct delay syntax

   In Verilog, the correct syntax to delay is #time; where time is a number representing delay units.

2. Step 2: Match options to syntax

   #10; matches the correct syntax: #10;. Options A, C, and D are incorrect because they misuse keywords or add extra words.

3. Final Answer:

   #10; -> Option D

4. Quick Check:

   Delay syntax = #time; = B [OK]

Hint: Delay uses # followed directly by number and semicolon [OK]

Common Mistakes:

• Adding extra words after #delay
• Using #delay keyword instead of #number
• Missing semicolon after delay

3. What will be the output time sequence of the following Verilog code snippet?

initial begin
  $display("Time: %0t", $time);
  #5;
  $display("Time after delay: %0t", $time);
end

medium

A. Time: 0
Time after delay: 0

B. Time: 5
Time after delay: 10

C. Time: 0
Time after delay: 5

D. Time: 5
Time after delay: 5

Solution

1. Step 1: Understand initial time and delay effect

   The simulation starts at time 0. The first $display prints time 0. Then #5; delays simulation by 5 time units.

2. Step 2: Determine time after delay

   After the delay, the second $display prints the current time, which is 5.

3. Final Answer:

   Time: 0 Time after delay: 5 -> Option C

4. Quick Check:

   Initial time 0 + #5 delay = 5 [OK]

Hint: First print at 0, second after #5 delay at time 5 [OK]

Common Mistakes:

• Assuming time does not advance after #delay
• Printing time before delay as non-zero
• Confusing delay units with clock cycles

4. Identify the error in this Verilog code snippet using #delay:

initial begin
  #10
  $display("Delayed output");
end

medium

A. Incorrect use of $display

B. Missing semicolon after #10

C. Delay value must be in parentheses

D. initial block cannot have delays

Solution

1. Step 1: Check syntax of delay statement

   The delay statement #10 must be followed by a semicolon to separate it from the next statement.

2. Step 2: Verify other statements

   The $display statement is correct, delay values do not require parentheses, and initial blocks can have delays.

3. Final Answer:

   Missing semicolon after #10 -> Option B

4. Quick Check:

   Delay statements need semicolon = A [OK]

Hint: Always put semicolon after #delay number [OK]

Common Mistakes:

• Omitting semicolon after delay
• Adding parentheses around delay number
• Thinking delays not allowed in initial blocks

5. Given the following code, what will be the output times printed?

initial begin
  $display("Start time: %0t", $time);
  #3;
  $display("After first delay: %0t", $time);
  #2;
  $display("After second delay: %0t", $time);
end

Assuming timescale is 1ns / 1ps.

hard

A. Start time: 0
After first delay: 3
After second delay: 5

B. Start time: 0
After first delay: 2
After second delay: 4

C. Start time: 1
After first delay: 4
After second delay: 6

D. Start time: 0
After first delay: 5
After second delay: 7

Solution

1. Step 1: Analyze initial time and first delay

   The simulation starts at time 0. The first $display prints 0. Then #3; delays simulation by 3 time units, so time becomes 3.

2. Step 2: Analyze second delay and final time

   After printing time 3, the next #2; adds 2 more units, making time 5. The last $display prints 5.

3. Final Answer:

   Start time: 0 After first delay: 3 After second delay: 5 -> Option A

4. Quick Check:

   0 + 3 + 2 = 5 time units [OK]

Hint: Add delays cumulatively to get output times [OK]

Common Mistakes:

• Adding delays incorrectly or skipping first time 0
• Confusing timescale units
• Assuming delays reset time