Simulation time control with #delay in Verilog - Step-by-Step Execution

Concept Flow - Simulation time control with #delay

Start simulation

↓

Execute statement

↓

#delay encountered?

No→Execute next statement

Yes↓

Wait for delay time

↓

Resume execution after delay

↓

Repeat until end

The simulation runs statements in order, pauses when a #delay is found, waits that time, then continues.

Execution Sample

Verilog

initial begin
  a = 0;
  #5 a = 1;
  #10 a = 0;
end

This code sets 'a' to 0, waits 5 time units, sets 'a' to 1, waits 10 time units, then sets 'a' back to 0.

Execution Table

Step	Simulation Time	Statement	Action	Variable 'a' Value
1	0	a = 0;	Assign 0 to a	0
2	0	#5 delay;	Wait 5 time units	0
3	5	a = 1;	Assign 1 to a	1
4	5	#10 delay;	Wait 10 time units	1
5	15	a = 0;	Assign 0 to a	0
6	15	End of initial block	Simulation ends	0

💡 Simulation ends after last statement at time 15

Variable Tracker

Variable	Start (time 0)	After Step 1 (time 0)	After Step 3 (time 5)	After Step 5 (time 15)
a	x (undefined)	0	1	0

Key Moments - 3 Insights

Why does the simulation time jump from 0 to 5 after the #5 delay?

Because #5 means wait 5 time units before executing the next statement, so simulation time advances from 0 to 5 (see execution_table step 2 to 3).

Does the assignment happen immediately when the delay is specified?

No, the assignment happens only after the delay finishes. For example, 'a = 1;' happens at time 5 after waiting #5 (execution_table step 3).

What happens if there is no #delay between statements?

Statements execute at the same simulation time without advancing time, as in step 1 where 'a = 0;' happens at time 0 immediately.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of 'a' at simulation time 10?

A 0

B 1

C x (undefined)

D Simulation time 10 does not exist in the table

💡 Hint

Check the variable_tracker and execution_table rows for time 5 and 15; 'a' is 1 from time 5 until time 15.

At which step does the simulation time advance from 5 to 15?

A Step 2

B Step 3

C Step 4

D Step 5

💡 Hint

Look at execution_table step 4 where #10 delay causes time to jump from 5 to 15.

If the #10 delay was changed to #3 delay at step 4, what would be the new simulation time at step 5?

A 8

B 13

C 15

D 18

💡 Hint

Add the delay time to the previous simulation time: 5 + 3 = 8 (see execution_table step 4).

Concept Snapshot

Simulation time control with #delay in Verilog:
- #delay pauses simulation for specified time units.
- Statements before delay execute at current time.
- After delay, simulation time advances and next statement runs.
- Multiple delays add up simulation time.
- No delay means statements execute at same simulation time.

Full Transcript

This example shows how Verilog simulation uses #delay to control time. The variable 'a' is assigned 0 at time 0. Then the simulation waits 5 time units (#5), advancing time to 5, and assigns 'a' to 1. Next, it waits 10 time units (#10), advancing time to 15, and assigns 'a' back to 0. The execution table tracks each step with simulation time and variable values. The variable tracker shows how 'a' changes over time. Key moments clarify that delays cause simulation time to jump and assignments happen after delays. The visual quiz tests understanding of time advancement and variable values during simulation. This helps beginners see how #delay controls simulation timing step-by-step.

Practice

1. What does the #delay statement do in Verilog simulation?

easy

A. Pauses the simulation for a specified time before executing the next statement

B. Immediately ends the simulation

C. Skips the next statement without delay

D. Changes the clock frequency during simulation

Solution

1. Step 1: Understand the role of #delay

   The #delay statement in Verilog is used to pause the simulation for a certain amount of time before the next statement runs.

2. Step 2: Compare options with the definition

   Only Pauses the simulation for a specified time before executing the next statement correctly describes this behavior. Options A, B, and C describe unrelated or incorrect actions.

3. Final Answer:

   Pauses the simulation for a specified time before executing the next statement -> Option A

4. Quick Check:

   #delay pauses simulation = D [OK]

Hint: Remember: #delay waits before next action runs [OK]

Common Mistakes:

• Thinking #delay ends simulation
• Confusing #delay with clock control
• Assuming #delay skips statements

2. Which of the following is the correct syntax to delay 10 time units in Verilog?

easy

A. #10 delay;

B. #delay 10;

C. delay #10;

D. #10;

Solution

1. Step 1: Recall correct delay syntax

   In Verilog, the correct syntax to delay is #time; where time is a number representing delay units.

2. Step 2: Match options to syntax

   #10; matches the correct syntax: #10;. Options A, C, and D are incorrect because they misuse keywords or add extra words.

3. Final Answer:

   #10; -> Option D

4. Quick Check:

   Delay syntax = #time; = B [OK]

Hint: Delay uses # followed directly by number and semicolon [OK]

Common Mistakes:

• Adding extra words after #delay
• Using #delay keyword instead of #number
• Missing semicolon after delay

3. What will be the output time sequence of the following Verilog code snippet?

initial begin
  $display("Time: %0t", $time);
  #5;
  $display("Time after delay: %0t", $time);
end

medium

A. Time: 0
Time after delay: 0

B. Time: 5
Time after delay: 10

C. Time: 0
Time after delay: 5

D. Time: 5
Time after delay: 5

Solution

1. Step 1: Understand initial time and delay effect

   The simulation starts at time 0. The first $display prints time 0. Then #5; delays simulation by 5 time units.

2. Step 2: Determine time after delay

   After the delay, the second $display prints the current time, which is 5.

3. Final Answer:

   Time: 0 Time after delay: 5 -> Option C

4. Quick Check:

   Initial time 0 + #5 delay = 5 [OK]

Hint: First print at 0, second after #5 delay at time 5 [OK]

Common Mistakes:

• Assuming time does not advance after #delay
• Printing time before delay as non-zero
• Confusing delay units with clock cycles

4. Identify the error in this Verilog code snippet using #delay:

initial begin
  #10
  $display("Delayed output");
end

medium

A. Incorrect use of $display

B. Missing semicolon after #10

C. Delay value must be in parentheses

D. initial block cannot have delays

Solution

1. Step 1: Check syntax of delay statement

   The delay statement #10 must be followed by a semicolon to separate it from the next statement.

2. Step 2: Verify other statements

   The $display statement is correct, delay values do not require parentheses, and initial blocks can have delays.

3. Final Answer:

   Missing semicolon after #10 -> Option B

4. Quick Check:

   Delay statements need semicolon = A [OK]

Hint: Always put semicolon after #delay number [OK]

Common Mistakes:

• Omitting semicolon after delay
• Adding parentheses around delay number
• Thinking delays not allowed in initial blocks

5. Given the following code, what will be the output times printed?

initial begin
  $display("Start time: %0t", $time);
  #3;
  $display("After first delay: %0t", $time);
  #2;
  $display("After second delay: %0t", $time);
end

Assuming timescale is 1ns / 1ps.

hard

A. Start time: 0
After first delay: 3
After second delay: 5

B. Start time: 0
After first delay: 2
After second delay: 4

C. Start time: 1
After first delay: 4
After second delay: 6

D. Start time: 0
After first delay: 5
After second delay: 7

Solution

1. Step 1: Analyze initial time and first delay

   The simulation starts at time 0. The first $display prints 0. Then #3; delays simulation by 3 time units, so time becomes 3.

2. Step 2: Analyze second delay and final time

   After printing time 3, the next #2; adds 2 more units, making time 5. The last $display prints 5.

3. Final Answer:

   Start time: 0 After first delay: 3 After second delay: 5 -> Option A

4. Quick Check:

   0 + 3 + 2 = 5 time units [OK]

Hint: Add delays cumulatively to get output times [OK]

Common Mistakes:

• Adding delays incorrectly or skipping first time 0
• Confusing timescale units
• Assuming delays reset time