Parameters are declared using the keyword parameter followed by the name and value, without specifying type keywords like int or integer.
Step 2: Check each option
parameter WIDTH = 8; uses correct syntax. The other options incorrectly add type keywords like int or integer.
Final Answer:
parameter WIDTH = 8; -> Option A
Quick Check:
Simple parameter syntax = A [OK]
Hint: Parameters use just 'parameter' keyword, no type needed [OK]
Common Mistakes:
Adding 'int' or 'integer' keywords with parameter
Using semicolon incorrectly
Confusing parameter with variable declaration
3. What is the output of this Verilog code snippet?
module test;
integer count = 5;
parameter MAX = 10;
initial begin
count = count + 3;
$display("Count: %0d, Max: %0d", count, MAX);
end
endmodule
medium
A. Count: 8, Max: 10
B. Count: 5, Max: 10
C. Count: 8, Max: 8
D. Syntax error
Solution
Step 1: Trace the integer variable update
The integer count starts at 5 and is incremented by 3, so it becomes 8.
Step 2: Check the parameter value
The parameter MAX is set to 10 and remains unchanged.
Final Answer:
Count: 8, Max: 10 -> Option A
Quick Check:
5 + 3 = 8, MAX = 10 [OK]
Hint: Parameters stay fixed; integers can be updated [OK]
Common Mistakes:
Assuming parameter MAX changes
Forgetting to add 3 to count
Thinking code causes syntax error
4. Identify the error in this Verilog code:
module example;
parameter SIZE = 4;
integer i;
initial begin
for (i = 0; i < SIZE; i = i + 1)
$display("i = %0d", i);
SIZE = 10;
end
endmodule
medium
A. Parameter SIZE must be declared as integer
B. Integer i cannot be used in for loop
C. Cannot assign a new value to parameter SIZE
D. Missing semicolon after for loop
Solution
Step 1: Check parameter assignment
Parameters are constants and cannot be assigned new values after declaration. The line SIZE = 10; causes an error.
Step 2: Verify other parts
Using integer i in a for loop is valid. Semicolons are correct. Parameter does not need to be declared as integer.
Final Answer:
Cannot assign a new value to parameter SIZE -> Option C
Quick Check:
Parameters are constant [OK]
Hint: Parameters cannot be changed after declaration [OK]
Common Mistakes:
Trying to assign new value to parameter
Thinking integer can't be loop variable
Ignoring semicolon placement
5. You want to create a Verilog module that uses a parameter to set the size of an integer array, but also needs a variable integer to count how many elements are used during simulation. Which is the best way to declare these?