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Verilogprogramming~5 mins

Using $display and $monitor in Verilog

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Introduction

$display and $monitor help you see what is happening inside your Verilog code while it runs. They show values of signals so you can understand and check your design.

You want to print the value of signals at a specific moment in simulation.
You want to watch signals and see their values whenever they change.
You are debugging your design and need to check if signals behave as expected.
You want to log signal values to understand the flow of your circuit.
You want to compare outputs at different times during simulation.
Syntax
Verilog
$display("format string", variables);
$monitor("format string", variables);

$display prints once when it is called.

$monitor prints automatically whenever any variable in its list changes.

Examples
Prints the current simulation time and values of signals a and b once when this line runs.
Verilog
$display("Time=%0t, a=%b, b=%b", $time, a, b);
Automatically prints the values of x and y every time either x or y changes.
Verilog
$monitor("At time %0t: x=%d, y=%d", $time, x, y);
Sample Program

This program uses $monitor to print the values of a and b whenever they change. It shows how $monitor automatically updates output on signal changes.

Verilog
module test;
  reg a, b;
  initial begin
    $monitor("At time %0t: a=%b, b=%b", $time, a, b);
    a = 0; b = 0;
    #5 a = 1;
    #5 b = 1;
    #5 a = 0;
    #5 $finish;
  end
endmodule
OutputSuccess
Important Notes

$display is like taking a snapshot at one moment.

$monitor keeps watching and prints whenever something changes.

You can use format specifiers like %b for binary, %d for decimal, and %0t for time.

Summary

$display prints once when called, useful for single messages.

$monitor prints automatically on changes, useful for watching signals.

Both help you understand what your Verilog code is doing during simulation.

Practice

(1/5)
1. What is the main difference between $display and $monitor in Verilog?
easy
A. $display prints continuously; $monitor prints only once.
B. $display prints once when called; $monitor prints whenever a variable changes.
C. $display is used for debugging; $monitor is used for synthesis.
D. $display prints to a file; $monitor prints to the console.

Solution

  1. Step 1: Understand $display behavior

    $display prints a message only once at the time it is called during simulation.

  2. Step 2: Understand $monitor behavior

    $monitor automatically prints a message every time any of the monitored variables change value.

  3. Final Answer:

    $display prints once when called; $monitor prints whenever a variable changes. -> Option B

  4. Quick Check:

    $display = once, $monitor = on change [OK]
Hint: Remember: display = one-time print, monitor = auto on change [OK]
Common Mistakes:
  • Thinking $display prints continuously
  • Confusing $monitor with file output
  • Assuming $monitor prints only once
2. Which of the following is the correct syntax to print the value of a 4-bit register reg [3:0] count; using $display?
easy
A. $display("Count value: %d", count);
B. $display("Count value: %h", count);
C. $display("Count value: %s", count);
D. $display("Count value: %b", count);

Solution

  1. Step 1: Identify the data type and format specifier

    The register count is 4-bit binary, so binary format specifier %b is appropriate.

  2. Step 2: Match format specifier with $display syntax

    $display("Count value: %b", count); correctly prints the binary value of count.

  3. Final Answer:

    $display("Count value: %b", count); -> Option D

  4. Quick Check:

    Binary format = %b [OK]
Hint: Use %b for binary, %d decimal, %h hex in $display [OK]
Common Mistakes:
  • Using %s which is for strings, not numbers
  • Using %d for binary values
  • Forgetting to include variable after format string
3. Given the following Verilog code snippet, what will be the output during simulation? 
reg [1:0] a;
initial begin
  a = 2'b00;
  $monitor("Time=%0t a=%b", $time, a);
  #5 a = 2'b01;
  #5 a = 2'b11;
  #5 a = 2'b10;
end
medium
A. Prints four lines showing time and value of 'a' at 0, 5, 10, and 15 time units.
B. Prints only one line at time 0 with initial value of 'a'.
C. Prints three lines at times 5, 10, and 15 but not at time 0.
D. No output because $monitor is not called correctly.

Solution

  1. Step 1: Understand $monitor initial print

    $monitor prints immediately when called (time 0) and then whenever monitored variables change.

  2. Step 2: Trace changes to 'a' and timing

    'a' changes at 5, 10, and 15 time units, so $monitor prints at these times plus initial time 0.

  3. Final Answer:

    Prints four lines showing time and value of 'a' at 0, 5, 10, and 15 time units. -> Option A

  4. Quick Check:

    $monitor prints on call + changes = 4 prints [OK]
Hint: $monitor prints immediately and on every change [OK]
Common Mistakes:
  • Assuming $monitor prints only on changes, missing initial print
  • Thinking $monitor prints only once
  • Confusing $display behavior with $monitor
4. Identify the error in this Verilog code snippet: 
reg clk;
initial begin
  $monitor("Clock = %b", clk);
  clk = 0;
  #10 clk = 1;
  #10 clk = 0;
end
medium
A. clk should be declared as wire, not reg, for $monitor to work.
B. Missing semicolon after $monitor statement causes syntax error.
C. $monitor is called before clk is initialized, so initial print shows unknown value.
D. No error; code runs and prints correctly.

Solution

  1. Step 1: Check order of $monitor and variable initialization

    $monitor is called before clk is assigned a value, so initial print shows 'x' (unknown).

  2. Step 2: Understand $monitor initial print behavior

    $monitor prints immediately on call, so it prints clk's value before initialization.

  3. Final Answer:

    $monitor is called before clk is initialized, so initial print shows unknown value. -> Option C

  4. Quick Check:

    Initialize variables before $monitor call [OK]
Hint: Initialize variables before $monitor to avoid unknown prints [OK]
Common Mistakes:
  • Assuming $monitor waits for variable initialization
  • Thinking missing semicolon causes error here
  • Confusing reg and wire for $monitor usage
5. You want to monitor two signals reg [3:0] data; and reg valid; so that the simulation prints their values only when valid changes. Which is the best way to do this using $monitor?
hard
A. $monitor("Data=%b Valid=%b", data, valid);
B. Use an if statement inside $monitor to print only when valid changes.
C. Use $monitor with only valid variable: $monitor("Valid=%b", valid); and add $display for data.
D. Use $monitor with both variables but assign data only when valid changes.

Solution

  1. Step 1: Understand $monitor behavior with multiple variables

    $monitor prints whenever any monitored variable changes. Monitoring both data and valid prints on either change.

  2. Step 2: Restrict printing to valid changes only

    To print only when valid changes, monitor only valid. But then data won't print updated values automatically.

  3. Step 3: Best practical approach

    Monitoring both variables prints all changes, but since data changes only when valid changes, this works well. $monitor("Data=%b Valid=%b", data, valid); is simplest and correct.

  4. Final Answer:

    $monitor("Data=%b Valid=%b", data, valid); -> Option A

  5. Quick Check:

    Monitor all needed vars; prints on any change [OK]
Hint: Monitor all variables to track changes together [OK]
Common Mistakes:
  • Trying to put conditions inside $monitor (not allowed)
  • Monitoring only one variable and missing others' changes
  • Using $display inside $monitor incorrectly
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