Simulation time control with #delay in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What does the #delay statement do in Verilog simulation?

It pauses the simulation for a specified amount of time before executing the next statement. This helps control when events happen in the simulation.

beginner

How do you write a 10-time unit delay before assigning a value to a signal out?

You write:
#10 out = 1;
This means wait 10 time units, then set out to 1.

intermediate

What is the difference between #delay and wait in Verilog?

#delay pauses for a fixed time. wait pauses until a condition becomes true.
Example: #5 waits 5 units, wait(signal == 1) waits until signal is 1.

beginner

Can #delay be used inside an initial block? What is its effect?

Yes. Inside an initial block, #delay controls when statements run during simulation start. It helps create timed test sequences.

intermediate

What happens if you write multiple #delay statements in sequence?

The delays add up. For example, #5; #10; means wait 5 units, then wait 10 more units, totaling 15 units before the next statement.

What does #20 mean in a Verilog simulation?

A Wait 20 time units before next statement

B Repeat next statement 20 times

C Set signal to 20

D End simulation after 20 cycles

#20 pauses simulation for 20 time units before continuing.

Which block commonly uses #delay to create test sequences?

A <code>initial</code> block

B <code>always</code> block

C <code>module</code> declaration

D <code>assign</code> statement

initial blocks run once at simulation start and often use #delay for timing.

What is the total delay of #5; #10; executed in sequence?

A 5 time units

B 10 time units

C 15 time units

D Cannot be determined

Delays add up, so total is 5 + 10 = 15 time units.

Which statement is true about #delay in Verilog?

A It waits for a condition to be true

B It pauses simulation for a fixed time

C It triggers an interrupt

D It resets the simulation time

#delay pauses simulation for a fixed amount of time.

If you want to wait until a signal ready is high, which is better than #delay?

A <code>assign ready = 1;</code>

B <code>#10;</code>

C <code>initial begin</code>

D <code>wait (ready == 1);</code>

wait waits for a condition, unlike #delay which waits fixed time.

Explain how #delay controls simulation time in Verilog and give an example.

Think about how you tell a story with pauses.

Describe the difference between #delay and wait statements in Verilog simulation.

One is like waiting a set time, the other waits for a signal.

Practice

1. What does the #delay statement do in Verilog simulation?

easy

A. Pauses the simulation for a specified time before executing the next statement

B. Immediately ends the simulation

C. Skips the next statement without delay

D. Changes the clock frequency during simulation

Solution

1. Step 1: Understand the role of #delay

   The #delay statement in Verilog is used to pause the simulation for a certain amount of time before the next statement runs.

2. Step 2: Compare options with the definition

   Only Pauses the simulation for a specified time before executing the next statement correctly describes this behavior. Options A, B, and C describe unrelated or incorrect actions.

3. Final Answer:

   Pauses the simulation for a specified time before executing the next statement -> Option A

4. Quick Check:

   #delay pauses simulation = D [OK]

Hint: Remember: #delay waits before next action runs [OK]

Common Mistakes:

• Thinking #delay ends simulation
• Confusing #delay with clock control
• Assuming #delay skips statements

2. Which of the following is the correct syntax to delay 10 time units in Verilog?

easy

A. #10 delay;

B. #delay 10;

C. delay #10;

D. #10;

Solution

1. Step 1: Recall correct delay syntax

   In Verilog, the correct syntax to delay is #time; where time is a number representing delay units.

2. Step 2: Match options to syntax

   #10; matches the correct syntax: #10;. Options A, C, and D are incorrect because they misuse keywords or add extra words.

3. Final Answer:

   #10; -> Option D

4. Quick Check:

   Delay syntax = #time; = B [OK]

Hint: Delay uses # followed directly by number and semicolon [OK]

Common Mistakes:

• Adding extra words after #delay
• Using #delay keyword instead of #number
• Missing semicolon after delay

3. What will be the output time sequence of the following Verilog code snippet?

initial begin
  $display("Time: %0t", $time);
  #5;
  $display("Time after delay: %0t", $time);
end

medium

A. Time: 0
Time after delay: 0

B. Time: 5
Time after delay: 10

C. Time: 0
Time after delay: 5

D. Time: 5
Time after delay: 5

Solution

1. Step 1: Understand initial time and delay effect

   The simulation starts at time 0. The first $display prints time 0. Then #5; delays simulation by 5 time units.

2. Step 2: Determine time after delay

   After the delay, the second $display prints the current time, which is 5.

3. Final Answer:

   Time: 0 Time after delay: 5 -> Option C

4. Quick Check:

   Initial time 0 + #5 delay = 5 [OK]

Hint: First print at 0, second after #5 delay at time 5 [OK]

Common Mistakes:

• Assuming time does not advance after #delay
• Printing time before delay as non-zero
• Confusing delay units with clock cycles

4. Identify the error in this Verilog code snippet using #delay:

initial begin
  #10
  $display("Delayed output");
end

medium

A. Incorrect use of $display

B. Missing semicolon after #10

C. Delay value must be in parentheses

D. initial block cannot have delays

Solution

1. Step 1: Check syntax of delay statement

   The delay statement #10 must be followed by a semicolon to separate it from the next statement.

2. Step 2: Verify other statements

   The $display statement is correct, delay values do not require parentheses, and initial blocks can have delays.

3. Final Answer:

   Missing semicolon after #10 -> Option B

4. Quick Check:

   Delay statements need semicolon = A [OK]

Hint: Always put semicolon after #delay number [OK]

Common Mistakes:

• Omitting semicolon after delay
• Adding parentheses around delay number
• Thinking delays not allowed in initial blocks

5. Given the following code, what will be the output times printed?

initial begin
  $display("Start time: %0t", $time);
  #3;
  $display("After first delay: %0t", $time);
  #2;
  $display("After second delay: %0t", $time);
end

Assuming timescale is 1ns / 1ps.

hard

A. Start time: 0
After first delay: 3
After second delay: 5

B. Start time: 0
After first delay: 2
After second delay: 4

C. Start time: 1
After first delay: 4
After second delay: 6

D. Start time: 0
After first delay: 5
After second delay: 7

Solution

1. Step 1: Analyze initial time and first delay

   The simulation starts at time 0. The first $display prints 0. Then #3; delays simulation by 3 time units, so time becomes 3.

2. Step 2: Analyze second delay and final time

   After printing time 3, the next #2; adds 2 more units, making time 5. The last $display prints 5.

3. Final Answer:

   Start time: 0 After first delay: 3 After second delay: 5 -> Option A

4. Quick Check:

   0 + 3 + 2 = 5 time units [OK]

Hint: Add delays cumulatively to get output times [OK]

Common Mistakes:

• Adding delays incorrectly or skipping first time 0
• Confusing timescale units
• Assuming delays reset time