Initial block for stimulus in Verilog - Step-by-Step Execution

Concept Flow - Initial block for stimulus

Start simulation

↓

Execute initial block

↓

Set initial values

↓

Wait for time or events

↓

Change signals as stimulus

↓

End initial block

↓

Simulation continues or stops

The initial block runs once at simulation start, setting signals and applying stimulus over time.

Execution Sample

Verilog

initial begin
  clk = 0;
  reset = 1;
  #10 reset = 0;
end

This code sets clk to 0, asserts reset for 10 time units, then deasserts reset.

Execution Table

Step	Time	Action	Signal	Value
1	0	Set clk to 0	clk	0
2	0	Set reset to 1	reset	1
3	10	After delay #10, set reset to 0	reset	0
4	10+	Initial block ends	-	-

💡 Initial block completes after all statements and delays execute once.

Variable Tracker

Signal	Time 0	Time 10	Final
clk	0	0	0
reset	1	0	0

Key Moments - 3 Insights

Why does the initial block run only once?

Because initial blocks in Verilog execute once at simulation start, as shown by the single pass in the execution_table.

What does the #10 delay mean in the initial block?

It means wait 10 time units before executing the next statement, as seen between steps 2 and 3 in the execution_table.

Why does clk stay 0 throughout the initial block?

Because clk is set once at time 0 and not changed later in the initial block, shown in variable_tracker.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of reset at time 0?

A Undefined

B 0

C 1

D It changes continuously

💡 Hint

Check step 2 in execution_table where reset is set to 1 at time 0.

At which step does reset change from 1 to 0?

A Step 1

B Step 3

C Step 2

D Step 4

💡 Hint

Look at step 3 in execution_table where reset is set to 0 after #10 delay.

If we add 'clk = 1;' after '#10 reset = 0;', what would clk be at time 10?

A 1

B Undefined

C 0

D It toggles continuously

💡 Hint

Adding 'clk = 1;' after delay changes clk at time 10, check variable_tracker logic.

Concept Snapshot

initial begin
  // statements
  signal = value;
  #delay signal = new_value;
end

- Runs once at simulation start
- Used to set initial signals and apply stimulus
- Delays (#) pause simulation time before next statement

Full Transcript

In Verilog, the initial block runs once at the start of simulation. It sets signals to initial values and can apply stimulus using delays. For example, clk is set to 0 and reset is set to 1 at time 0. After 10 time units, reset is set to 0. The initial block then ends. Variables keep their last assigned values unless changed. Delays pause execution inside the initial block. This block is useful to start your simulation with known signal states and test inputs.

Practice

1. What is the main purpose of an initial block in Verilog?

easy

A. To set starting values and apply test signals during simulation

B. To describe hardware that runs continuously

C. To declare input and output ports

D. To synthesize the final hardware design

Solution

1. Step 1: Understand the role of initial blocks

   Initial blocks run once at the start of simulation to set initial conditions or apply test signals.

2. Step 2: Differentiate from other Verilog constructs

   Continuous hardware behavior is described by always blocks, not initial blocks.

3. Final Answer:

   To set starting values and apply test signals during simulation -> Option A

4. Quick Check:

   Initial block = setup stimulus [OK]

Hint: Initial blocks run once at start to set test signals [OK]

Common Mistakes:

• Confusing initial with always blocks
• Thinking initial blocks synthesize hardware
• Assuming initial blocks run repeatedly

2. Which of the following is the correct syntax to start an initial block in Verilog?

easy

A. always begin ... end

B. module initial ... endmodule

C. initial begin ... end

D. start initial ... finish

Solution

1. Step 1: Recall Verilog initial block syntax

   An initial block starts with the keyword initial followed by a begin and ends with end.

2. Step 2: Eliminate incorrect options

   always is for continuous behavior, module and start/finish are invalid here.

3. Final Answer:

   initial begin ... end -> Option C

4. Quick Check:

   Initial block syntax = initial begin ... end [OK]

Hint: Initial blocks use 'initial begin' and 'end' [OK]

Common Mistakes:

• Using always instead of initial
• Confusing module declaration with initial block
• Using non-Verilog keywords like start/finish

3. What will be the value of signal at time 15 in this Verilog code?

reg signal;
initial begin
  signal = 0;
  #10 signal = 1;
  #10 signal = 0;
end

medium

A. Signal not declared

B. 0

C. Undefined (X)

D. 1

Solution

1. Step 1: Trace signal changes over time

   At time 0, signal = 0; at time 10, signal changes to 1; at time 20, signal changes back to 0.

2. Step 2: Determine signal value at time 15

   Time 15 is between 10 and 20, so signal is 1 during that interval.

3. Final Answer:

   1 -> Option D

4. Quick Check:

   Signal at 15 = 1 [OK]

Hint: Check delays (#) to find signal value at given time [OK]

Common Mistakes:

• Assuming signal changes immediately without delay
• Confusing time units or delay order
• Ignoring initial assignment

4. Identify the error in this initial block:

initial
  signal = 1;
  #5 signal = 0;
end

medium

A. Missing begin keyword after initial

B. Missing semicolon after signal assignment

C. Cannot use delays (#) inside initial blocks

D. signal is not declared as reg

Solution

1. Step 1: Check initial block structure

   When multiple statements or delays are used, initial must be followed by begin and ended with end.

2. Step 2: Identify missing keywords

   The code has end but no begin, causing syntax error.

3. Final Answer:

   Missing begin keyword after initial -> Option A

4. Quick Check:

   Multiple statements need begin-end [OK]

Hint: Use begin-end for multiple statements in initial [OK]

Common Mistakes:

• Omitting begin-end for multiple lines
• Thinking delays are not allowed in initial
• Forgetting to declare signal as reg

5. You want to create a stimulus that toggles a clock signal every 5 time units starting at 0. Which initial block correctly implements this?

hard

A. initial begin
clock = 0;
#5 clock = 1;
#5 clock = 0;
end

B. initial begin
clock = 0;
forever #5 clock = ~clock;
end

C. initial begin
clock = 0;
repeat (5) #5 clock = ~clock;
end

D. initial begin
clock = 0;
#10 clock = ~clock;
end

Solution

1. Step 1: Understand toggling clock behavior

   Clock toggling every 5 time units means it flips repeatedly with a delay of 5 units.

2. Step 2: Analyze each option

   initial begin clock = 0; forever #5 clock = ~clock; end uses forever loop with #5 delay and toggles clock continuously. initial begin clock = 0; #5 clock = 1; #5 clock = 0; end toggles only twice. initial begin clock = 0; repeat (5) #5 clock = ~clock; end toggles 5 times then stops. initial begin clock = 0; #10 clock = ~clock; end toggles once after 10 units.

3. Final Answer:

   initial begin clock = 0; forever #5 clock = ~clock; end -> Option B

4. Quick Check:

   Continuous toggle needs forever loop [OK]

Hint: Use forever loop with delay for continuous toggling [OK]

Common Mistakes:

• Using fixed number of toggles instead of forever
• Incorrect delay timing for toggling
• Not initializing clock before toggling