Initial block for stimulus in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of an initial block in Verilog?

An initial block is used to set up stimulus or initial conditions in a simulation. It runs once at the start of the simulation.

beginner

How many times does an initial block execute during simulation?

An initial block executes exactly once at the beginning of the simulation.

beginner

In Verilog, how do you create a delay inside an initial block?

You use the # symbol followed by a number to specify delay in time units, for example: #10; delays 10 time units.

intermediate

What happens if you have multiple initial blocks in a Verilog module?

All initial blocks start running concurrently at simulation time 0, each executing their statements once.

beginner

Write a simple initial block that sets a signal clk to 0, waits 5 time units, then sets it to 1.

initial begin
  clk = 0;
  #5;
  clk = 1;
end

What is the main use of an initial block in Verilog?

A To synthesize combinational logic

B To describe hardware that runs continuously

C To declare variables

D To provide stimulus or initial setup at simulation start

An initial block runs once at simulation start to provide stimulus or initial conditions.

How many times does an initial block execute during simulation?

A Once

B Multiple times

C Never

D Depends on clock cycles

An initial block executes exactly once at the beginning of simulation.

Which symbol is used to create a delay inside an initial block?

A &

B #

C @

D $

The # symbol followed by a number creates a delay in time units.

If you have two initial blocks in a module, how do they run?

A Concurrently, both start at time 0

B One after the other sequentially

C Only the first one runs

D They run randomly

All initial blocks start concurrently at simulation time 0.

What will this code do?

initial begin
  signal = 0;
  #10;
  signal = 1;
end

A Signal stays 0 forever

B Set signal to 1 immediately

C Set signal to 0, wait 10 time units, then set to 1

D Cause a syntax error

The code sets signal to 0, waits 10 time units, then sets it to 1.

Explain what an initial block is and how it is used to provide stimulus in Verilog simulations.

Think about how you start a test by setting initial values and waiting.

Describe how delays work inside an initial block and why they are important for stimulus generation.

Delays help you wait before changing signals, like waiting before pressing a button.

Practice

1. What is the main purpose of an initial block in Verilog?

easy

A. To set starting values and apply test signals during simulation

B. To describe hardware that runs continuously

C. To declare input and output ports

D. To synthesize the final hardware design

Solution

1. Step 1: Understand the role of initial blocks

   Initial blocks run once at the start of simulation to set initial conditions or apply test signals.

2. Step 2: Differentiate from other Verilog constructs

   Continuous hardware behavior is described by always blocks, not initial blocks.

3. Final Answer:

   To set starting values and apply test signals during simulation -> Option A

4. Quick Check:

   Initial block = setup stimulus [OK]

Hint: Initial blocks run once at start to set test signals [OK]

Common Mistakes:

• Confusing initial with always blocks
• Thinking initial blocks synthesize hardware
• Assuming initial blocks run repeatedly

2. Which of the following is the correct syntax to start an initial block in Verilog?

easy

A. always begin ... end

B. module initial ... endmodule

C. initial begin ... end

D. start initial ... finish

Solution

1. Step 1: Recall Verilog initial block syntax

   An initial block starts with the keyword initial followed by a begin and ends with end.

2. Step 2: Eliminate incorrect options

   always is for continuous behavior, module and start/finish are invalid here.

3. Final Answer:

   initial begin ... end -> Option C

4. Quick Check:

   Initial block syntax = initial begin ... end [OK]

Hint: Initial blocks use 'initial begin' and 'end' [OK]

Common Mistakes:

• Using always instead of initial
• Confusing module declaration with initial block
• Using non-Verilog keywords like start/finish

3. What will be the value of signal at time 15 in this Verilog code?

reg signal;
initial begin
  signal = 0;
  #10 signal = 1;
  #10 signal = 0;
end

medium

A. Signal not declared

B. 0

C. Undefined (X)

D. 1

Solution

1. Step 1: Trace signal changes over time

   At time 0, signal = 0; at time 10, signal changes to 1; at time 20, signal changes back to 0.

2. Step 2: Determine signal value at time 15

   Time 15 is between 10 and 20, so signal is 1 during that interval.

3. Final Answer:

   1 -> Option D

4. Quick Check:

   Signal at 15 = 1 [OK]

Hint: Check delays (#) to find signal value at given time [OK]

Common Mistakes:

• Assuming signal changes immediately without delay
• Confusing time units or delay order
• Ignoring initial assignment

4. Identify the error in this initial block:

initial
  signal = 1;
  #5 signal = 0;
end

medium

A. Missing begin keyword after initial

B. Missing semicolon after signal assignment

C. Cannot use delays (#) inside initial blocks

D. signal is not declared as reg

Solution

1. Step 1: Check initial block structure

   When multiple statements or delays are used, initial must be followed by begin and ended with end.

2. Step 2: Identify missing keywords

   The code has end but no begin, causing syntax error.

3. Final Answer:

   Missing begin keyword after initial -> Option A

4. Quick Check:

   Multiple statements need begin-end [OK]

Hint: Use begin-end for multiple statements in initial [OK]

Common Mistakes:

• Omitting begin-end for multiple lines
• Thinking delays are not allowed in initial
• Forgetting to declare signal as reg

5. You want to create a stimulus that toggles a clock signal every 5 time units starting at 0. Which initial block correctly implements this?

hard

A. initial begin
clock = 0;
#5 clock = 1;
#5 clock = 0;
end

B. initial begin
clock = 0;
forever #5 clock = ~clock;
end

C. initial begin
clock = 0;
repeat (5) #5 clock = ~clock;
end

D. initial begin
clock = 0;
#10 clock = ~clock;
end

Solution

1. Step 1: Understand toggling clock behavior

   Clock toggling every 5 time units means it flips repeatedly with a delay of 5 units.

2. Step 2: Analyze each option

   initial begin clock = 0; forever #5 clock = ~clock; end uses forever loop with #5 delay and toggles clock continuously. initial begin clock = 0; #5 clock = 1; #5 clock = 0; end toggles only twice. initial begin clock = 0; repeat (5) #5 clock = ~clock; end toggles 5 times then stops. initial begin clock = 0; #10 clock = ~clock; end toggles once after 10 units.

3. Final Answer:

   initial begin clock = 0; forever #5 clock = ~clock; end -> Option B

4. Quick Check:

   Continuous toggle needs forever loop [OK]

Hint: Use forever loop with delay for continuous toggling [OK]

Common Mistakes:

• Using fixed number of toggles instead of forever
• Incorrect delay timing for toggling
• Not initializing clock before toggling