Initial block for stimulus in Verilog - Mini Project: Build & Apply

Initial Block for Stimulus in Verilog

📖 Scenario: You are designing a simple digital circuit and want to test it by sending some signals. In Verilog, the initial block is used to create stimulus signals that change over time to check if your circuit works correctly.

🎯 Goal: Create a Verilog testbench that uses an initial block to send a sequence of signals to a 1-bit input called signal_in. You will set signal_in to 0 at the start, then change it to 1 after some time, and then back to 0.

📋 What You'll Learn

Create a 1-bit register called signal_in

Use an initial block to set signal_in to 0 at time 0

Change signal_in to 1 after 10 time units

Change signal_in back to 0 after another 10 time units

Use $display to print the value of signal_in at each change

💡 Why This Matters

🌍 Real World

Initial blocks are used in testbenches to simulate how digital circuits respond to input signals over time.

💼 Career

Understanding stimulus generation in Verilog is essential for hardware engineers and verification engineers who test and validate digital designs.

1

Declare the 1-bit register signal_in

Write a line of Verilog code to declare a 1-bit register called signal_in.

Verilog

// Declare a 1-bit register called signal_in
// Your code here

Hint

Use the keyword reg to declare a register variable in Verilog.

2

Start the initial block and set signal_in to 0

Write an initial block that sets signal_in to 0 at the beginning.

Verilog

reg signal_in;

// Start initial block and set signal_in to 0
// Your code here

Hint

Use initial begin and end to create the block. Assign 0 to signal_in inside.

3

Add delays to change signal_in to 1 and then back to 0

Inside the initial block, after setting signal_in to 0, add a delay of 10 time units, then set signal_in to 1. After another 10 time units, set signal_in back to 0.

Verilog

reg signal_in;

initial begin
    signal_in = 0;
    // Add delay of 10 time units and set signal_in to 1
    // Add another delay of 10 time units and set signal_in to 0
    // Your code here
end

Hint

Use #10 to wait 10 time units before changing the value.

4

Print the value of signal_in at each change using $display

Add $display statements inside the initial block to print the value of signal_in right after each assignment.

Verilog

reg signal_in;

initial begin
    signal_in = 0;
    // Print signal_in value here
    #10 signal_in = 1;
    // Print signal_in value here
    #10 signal_in = 0;
    // Print signal_in value here
end

Hint

Use $display("Time %0t: signal_in = %b", $time, signal_in); to print the current time and value.

Practice

1. What is the main purpose of an initial block in Verilog?

easy

A. To set starting values and apply test signals during simulation

B. To describe hardware that runs continuously

C. To declare input and output ports

D. To synthesize the final hardware design

Solution

1. Step 1: Understand the role of initial blocks

   Initial blocks run once at the start of simulation to set initial conditions or apply test signals.

2. Step 2: Differentiate from other Verilog constructs

   Continuous hardware behavior is described by always blocks, not initial blocks.

3. Final Answer:

   To set starting values and apply test signals during simulation -> Option A

4. Quick Check:

   Initial block = setup stimulus [OK]

Hint: Initial blocks run once at start to set test signals [OK]

Common Mistakes:

• Confusing initial with always blocks
• Thinking initial blocks synthesize hardware
• Assuming initial blocks run repeatedly

2. Which of the following is the correct syntax to start an initial block in Verilog?

easy

A. always begin ... end

B. module initial ... endmodule

C. initial begin ... end

D. start initial ... finish

Solution

1. Step 1: Recall Verilog initial block syntax

   An initial block starts with the keyword initial followed by a begin and ends with end.

2. Step 2: Eliminate incorrect options

   always is for continuous behavior, module and start/finish are invalid here.

3. Final Answer:

   initial begin ... end -> Option C

4. Quick Check:

   Initial block syntax = initial begin ... end [OK]

Hint: Initial blocks use 'initial begin' and 'end' [OK]

Common Mistakes:

• Using always instead of initial
• Confusing module declaration with initial block
• Using non-Verilog keywords like start/finish

3. What will be the value of signal at time 15 in this Verilog code?

reg signal;
initial begin
  signal = 0;
  #10 signal = 1;
  #10 signal = 0;
end

medium

A. Signal not declared

B. 0

C. Undefined (X)

D. 1

Solution

1. Step 1: Trace signal changes over time

   At time 0, signal = 0; at time 10, signal changes to 1; at time 20, signal changes back to 0.

2. Step 2: Determine signal value at time 15

   Time 15 is between 10 and 20, so signal is 1 during that interval.

3. Final Answer:

   1 -> Option D

4. Quick Check:

   Signal at 15 = 1 [OK]

Hint: Check delays (#) to find signal value at given time [OK]

Common Mistakes:

• Assuming signal changes immediately without delay
• Confusing time units or delay order
• Ignoring initial assignment

4. Identify the error in this initial block:

initial
  signal = 1;
  #5 signal = 0;
end

medium

A. Missing begin keyword after initial

B. Missing semicolon after signal assignment

C. Cannot use delays (#) inside initial blocks

D. signal is not declared as reg

Solution

1. Step 1: Check initial block structure

   When multiple statements or delays are used, initial must be followed by begin and ended with end.

2. Step 2: Identify missing keywords

   The code has end but no begin, causing syntax error.

3. Final Answer:

   Missing begin keyword after initial -> Option A

4. Quick Check:

   Multiple statements need begin-end [OK]

Hint: Use begin-end for multiple statements in initial [OK]

Common Mistakes:

• Omitting begin-end for multiple lines
• Thinking delays are not allowed in initial
• Forgetting to declare signal as reg

5. You want to create a stimulus that toggles a clock signal every 5 time units starting at 0. Which initial block correctly implements this?

hard

A. initial begin
clock = 0;
#5 clock = 1;
#5 clock = 0;
end

B. initial begin
clock = 0;
forever #5 clock = ~clock;
end

C. initial begin
clock = 0;
repeat (5) #5 clock = ~clock;
end

D. initial begin
clock = 0;
#10 clock = ~clock;
end

Solution

1. Step 1: Understand toggling clock behavior

   Clock toggling every 5 time units means it flips repeatedly with a delay of 5 units.

2. Step 2: Analyze each option

   initial begin clock = 0; forever #5 clock = ~clock; end uses forever loop with #5 delay and toggles clock continuously. initial begin clock = 0; #5 clock = 1; #5 clock = 0; end toggles only twice. initial begin clock = 0; repeat (5) #5 clock = ~clock; end toggles 5 times then stops. initial begin clock = 0; #10 clock = ~clock; end toggles once after 10 units.

3. Final Answer:

   initial begin clock = 0; forever #5 clock = ~clock; end -> Option B

4. Quick Check:

   Continuous toggle needs forever loop [OK]

Hint: Use forever loop with delay for continuous toggling [OK]

Common Mistakes:

• Using fixed number of toggles instead of forever
• Incorrect delay timing for toggling
• Not initializing clock before toggling