Initial block for stimulus in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this initial block?

Consider the following Verilog code snippet. What will be the value of signal after the initial block finishes?

Verilog

module test;
  reg signal;
  initial begin
    signal = 0;
    #5 signal = 1;
    #10 signal = 0;
  end
endmodule

A signal = x (unknown)

B signal = 1

C signal = 0

D signal = z (high impedance)

💡 Hint

Think about the delays and the last assignment in the initial block.

The initial block sets signal to 0, then after 5 time units sets it to 1, then after 10 more time units sets it back to 0. The final value after the initial block completes is 0.

❓ Predict Output

intermediate

What is the value of count after this initial block?

Analyze this Verilog code. What value does count hold at the end of the initial block execution?

Verilog

module test;
  reg [3:0] count;
  initial begin
    count = 4'b0000;
    #2 count = count + 1;
    #3 count = count + 2;
  end
endmodule

A count = 0

B count = 2

C count = 1

D count = 3

💡 Hint

Add the increments step by step considering the delays.

Initially count is 0. After 2 time units, count becomes 1. After 3 more time units, count becomes 3 (1 + 2).

🔧 Debug

advanced

What error does this initial block cause?

Examine this Verilog code. What error will occur when simulating this initial block?

Verilog

module test;
  reg clk;
  initial begin
    clk = 0;
    #5 clk = 1;
  end
endmodule

A SyntaxError: missing semicolon

B RuntimeError: delay not allowed here

C No error, runs fine

D SyntaxError: unknown identifier

💡 Hint

Check the line endings carefully.

The first assignment line is missing a semicolon, causing a syntax error.

🧠 Conceptual

advanced

Which statement about initial blocks is true?

Select the correct statement about the behavior of initial blocks in Verilog.

A Initial blocks run only once at the start of simulation.

B Initial blocks run repeatedly in a loop during simulation.

C Initial blocks execute only when a clock edge occurs.

D Initial blocks are synthesizable hardware constructs.

💡 Hint

Think about when initial blocks execute in simulation.

Initial blocks run once at simulation start to provide stimulus or initialization. They do not loop or depend on clock edges and are generally not synthesizable.

❓ Predict Output

expert

What is the final value of data after this initial block?

Consider this Verilog code with multiple delays and assignments. What is the final value of data after the initial block completes?

Verilog

module test;
  reg [7:0] data;
  initial begin
    data = 8'hFF;
    #3 data = data >> 1;
    #2 data = data & 8'h0F;
    #1 data = data + 8'h01;
  end
endmodule

A data = 8'h07

B data = 8'h10

C data = 8'h0F

D data = 8'h08

💡 Hint

Calculate each step carefully considering bitwise operations and delays.

Initially, data = 8'hFF. After 3 time units, data = 8'hFF >> 1 = 8'h7F. After 2 more time units, data = 8'h7F & 8'h0F = 8'h0F. After 1 more time unit, data = 8'h0F + 8'h01 = 8'h10.

Practice

1. What is the main purpose of an initial block in Verilog?

easy

A. To set starting values and apply test signals during simulation

B. To describe hardware that runs continuously

C. To declare input and output ports

D. To synthesize the final hardware design

Solution

1. Step 1: Understand the role of initial blocks

   Initial blocks run once at the start of simulation to set initial conditions or apply test signals.

2. Step 2: Differentiate from other Verilog constructs

   Continuous hardware behavior is described by always blocks, not initial blocks.

3. Final Answer:

   To set starting values and apply test signals during simulation -> Option A

4. Quick Check:

   Initial block = setup stimulus [OK]

Hint: Initial blocks run once at start to set test signals [OK]

Common Mistakes:

• Confusing initial with always blocks
• Thinking initial blocks synthesize hardware
• Assuming initial blocks run repeatedly

2. Which of the following is the correct syntax to start an initial block in Verilog?

easy

A. always begin ... end

B. module initial ... endmodule

C. initial begin ... end

D. start initial ... finish

Solution

1. Step 1: Recall Verilog initial block syntax

   An initial block starts with the keyword initial followed by a begin and ends with end.

2. Step 2: Eliminate incorrect options

   always is for continuous behavior, module and start/finish are invalid here.

3. Final Answer:

   initial begin ... end -> Option C

4. Quick Check:

   Initial block syntax = initial begin ... end [OK]

Hint: Initial blocks use 'initial begin' and 'end' [OK]

Common Mistakes:

• Using always instead of initial
• Confusing module declaration with initial block
• Using non-Verilog keywords like start/finish

3. What will be the value of signal at time 15 in this Verilog code?

reg signal;
initial begin
  signal = 0;
  #10 signal = 1;
  #10 signal = 0;
end

medium

A. Signal not declared

B. 0

C. Undefined (X)

D. 1

Solution

1. Step 1: Trace signal changes over time

   At time 0, signal = 0; at time 10, signal changes to 1; at time 20, signal changes back to 0.

2. Step 2: Determine signal value at time 15

   Time 15 is between 10 and 20, so signal is 1 during that interval.

3. Final Answer:

   1 -> Option D

4. Quick Check:

   Signal at 15 = 1 [OK]

Hint: Check delays (#) to find signal value at given time [OK]

Common Mistakes:

• Assuming signal changes immediately without delay
• Confusing time units or delay order
• Ignoring initial assignment

4. Identify the error in this initial block:

initial
  signal = 1;
  #5 signal = 0;
end

medium

A. Missing begin keyword after initial

B. Missing semicolon after signal assignment

C. Cannot use delays (#) inside initial blocks

D. signal is not declared as reg

Solution

1. Step 1: Check initial block structure

   When multiple statements or delays are used, initial must be followed by begin and ended with end.

2. Step 2: Identify missing keywords

   The code has end but no begin, causing syntax error.

3. Final Answer:

   Missing begin keyword after initial -> Option A

4. Quick Check:

   Multiple statements need begin-end [OK]

Hint: Use begin-end for multiple statements in initial [OK]

Common Mistakes:

• Omitting begin-end for multiple lines
• Thinking delays are not allowed in initial
• Forgetting to declare signal as reg

5. You want to create a stimulus that toggles a clock signal every 5 time units starting at 0. Which initial block correctly implements this?

hard

A. initial begin
clock = 0;
#5 clock = 1;
#5 clock = 0;
end

B. initial begin
clock = 0;
forever #5 clock = ~clock;
end

C. initial begin
clock = 0;
repeat (5) #5 clock = ~clock;
end

D. initial begin
clock = 0;
#10 clock = ~clock;
end

Solution

1. Step 1: Understand toggling clock behavior

   Clock toggling every 5 time units means it flips repeatedly with a delay of 5 units.

2. Step 2: Analyze each option

   initial begin clock = 0; forever #5 clock = ~clock; end uses forever loop with #5 delay and toggles clock continuously. initial begin clock = 0; #5 clock = 1; #5 clock = 0; end toggles only twice. initial begin clock = 0; repeat (5) #5 clock = ~clock; end toggles 5 times then stops. initial begin clock = 0; #10 clock = ~clock; end toggles once after 10 units.

3. Final Answer:

   initial begin clock = 0; forever #5 clock = ~clock; end -> Option B

4. Quick Check:

   Continuous toggle needs forever loop [OK]

Hint: Use forever loop with delay for continuous toggling [OK]

Common Mistakes:

• Using fixed number of toggles instead of forever
• Incorrect delay timing for toggling
• Not initializing clock before toggling