Initial block for stimulus in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to start the initial block.

Verilog

initial begin
    [1]
end

Drag options to blanks, or click blank then click option'

Aclk = 0;

Balways @ (posedge clk);

Cmodule test();

Dassign clk = 1;

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'always' inside an initial block.

Trying to declare a module inside the initial block.

The initial block starts with 'initial begin' and inside you can assign initial values like 'clk = 0;'.

2fill in blank

medium

Complete the code to wait for 10 time units inside the initial block.

Verilog

initial begin
    #[1];
end

Drag options to blanks, or click blank then click option'

A5

B1

C20

D10

Attempts:

3 left

💡 Hint

Common Mistakes

Using a wrong delay value.

Forgetting the semicolon after the delay.

The delay operator '#' followed by a number waits that many time units. Here, '#10;' waits 10 time units.

3fill in blank

hard

Fix the error in the initial block to assign 1 to signal 'rst' after 5 time units.

Verilog

initial begin
    rst = 0;
    #[1] rst = 1;
end

Drag options to blanks, or click blank then click option'

A5

Brst

C;

D10

Attempts:

3 left

💡 Hint

Common Mistakes

Using a signal name instead of a number after '#'.

Missing the semicolon after the delay.

The delay operator '#' must be followed by a number and then a semicolon before the assignment. '#5 rst = 1;' is correct.

4fill in blank

hard

Fill both blanks to assign 0 to 'clk' and then toggle it after 5 time units.

Verilog

initial begin
    clk = [1];
    #[2] clk = ~clk;
end

Drag options to blanks, or click blank then click option'

A0

B5

C1

D10

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning clk to 1 initially.

Using wrong delay value.

Initially assign clk to 0, then after 5 time units toggle it with '~clk'.

5fill in blank

hard

Fill all three blanks to create an initial block that sets 'rst' to 1, waits 10 time units, then sets 'rst' to 0.

Verilog

initial begin
    rst = [1];
    #[2];
    rst = [3];
end

Drag options to blanks, or click blank then click option'

A0

B10

C1

D5

Attempts:

3 left

💡 Hint

Common Mistakes

Reversing the rst values.

Using wrong delay time.

Set rst to 1, wait 10 time units, then set rst to 0 to simulate a reset pulse.

Practice

1. What is the main purpose of an initial block in Verilog?

easy

A. To set starting values and apply test signals during simulation

B. To describe hardware that runs continuously

C. To declare input and output ports

D. To synthesize the final hardware design

Solution

1. Step 1: Understand the role of initial blocks

   Initial blocks run once at the start of simulation to set initial conditions or apply test signals.

2. Step 2: Differentiate from other Verilog constructs

   Continuous hardware behavior is described by always blocks, not initial blocks.

3. Final Answer:

   To set starting values and apply test signals during simulation -> Option A

4. Quick Check:

   Initial block = setup stimulus [OK]

Hint: Initial blocks run once at start to set test signals [OK]

Common Mistakes:

• Confusing initial with always blocks
• Thinking initial blocks synthesize hardware
• Assuming initial blocks run repeatedly

2. Which of the following is the correct syntax to start an initial block in Verilog?

easy

A. always begin ... end

B. module initial ... endmodule

C. initial begin ... end

D. start initial ... finish

Solution

1. Step 1: Recall Verilog initial block syntax

   An initial block starts with the keyword initial followed by a begin and ends with end.

2. Step 2: Eliminate incorrect options

   always is for continuous behavior, module and start/finish are invalid here.

3. Final Answer:

   initial begin ... end -> Option C

4. Quick Check:

   Initial block syntax = initial begin ... end [OK]

Hint: Initial blocks use 'initial begin' and 'end' [OK]

Common Mistakes:

• Using always instead of initial
• Confusing module declaration with initial block
• Using non-Verilog keywords like start/finish

3. What will be the value of signal at time 15 in this Verilog code?

reg signal;
initial begin
  signal = 0;
  #10 signal = 1;
  #10 signal = 0;
end

medium

A. Signal not declared

B. 0

C. Undefined (X)

D. 1

Solution

1. Step 1: Trace signal changes over time

   At time 0, signal = 0; at time 10, signal changes to 1; at time 20, signal changes back to 0.

2. Step 2: Determine signal value at time 15

   Time 15 is between 10 and 20, so signal is 1 during that interval.

3. Final Answer:

   1 -> Option D

4. Quick Check:

   Signal at 15 = 1 [OK]

Hint: Check delays (#) to find signal value at given time [OK]

Common Mistakes:

• Assuming signal changes immediately without delay
• Confusing time units or delay order
• Ignoring initial assignment

4. Identify the error in this initial block:

initial
  signal = 1;
  #5 signal = 0;
end

medium

A. Missing begin keyword after initial

B. Missing semicolon after signal assignment

C. Cannot use delays (#) inside initial blocks

D. signal is not declared as reg

Solution

1. Step 1: Check initial block structure

   When multiple statements or delays are used, initial must be followed by begin and ended with end.

2. Step 2: Identify missing keywords

   The code has end but no begin, causing syntax error.

3. Final Answer:

   Missing begin keyword after initial -> Option A

4. Quick Check:

   Multiple statements need begin-end [OK]

Hint: Use begin-end for multiple statements in initial [OK]

Common Mistakes:

• Omitting begin-end for multiple lines
• Thinking delays are not allowed in initial
• Forgetting to declare signal as reg

5. You want to create a stimulus that toggles a clock signal every 5 time units starting at 0. Which initial block correctly implements this?

hard

A. initial begin
clock = 0;
#5 clock = 1;
#5 clock = 0;
end

B. initial begin
clock = 0;
forever #5 clock = ~clock;
end

C. initial begin
clock = 0;
repeat (5) #5 clock = ~clock;
end

D. initial begin
clock = 0;
#10 clock = ~clock;
end

Solution

1. Step 1: Understand toggling clock behavior

   Clock toggling every 5 time units means it flips repeatedly with a delay of 5 units.

2. Step 2: Analyze each option

   initial begin clock = 0; forever #5 clock = ~clock; end uses forever loop with #5 delay and toggles clock continuously. initial begin clock = 0; #5 clock = 1; #5 clock = 0; end toggles only twice. initial begin clock = 0; repeat (5) #5 clock = ~clock; end toggles 5 times then stops. initial begin clock = 0; #10 clock = ~clock; end toggles once after 10 units.

3. Final Answer:

   initial begin clock = 0; forever #5 clock = ~clock; end -> Option B

4. Quick Check:

   Continuous toggle needs forever loop [OK]

Hint: Use forever loop with delay for continuous toggling [OK]

Common Mistakes:

• Using fixed number of toggles instead of forever
• Incorrect delay timing for toggling
• Not initializing clock before toggling