Encoder design in Verilog - Step-by-Step Execution

Concept Flow - Encoder design

Input signals

↓

Check which input is HIGH

↓

Assign binary code to output

↓

Output encoded binary

↓

End

The encoder checks which input line is active and outputs the corresponding binary code.

Execution Sample

Verilog

module encoder(
  input [3:0] in,
  output reg [1:0] out
);
  always @(*) begin
    case (in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'b00;
    endcase
  end
endmodule

This 4-to-2 encoder outputs a 2-bit binary code based on which single input bit is high.

Execution Table

Step	Input (in)	Condition Checked	Output (out)	Action
1	0001	in == 0001?	00	Output set to 00
2	0010	in == 0010?	01	Output set to 01
3	0100	in == 0100?	10	Output set to 10
4	1000	in == 1000?	11	Output set to 11
5	0000	No input high	00	Default output 00
6	0011	Multiple inputs high	00	Default output 00

💡 Stops after assigning output based on input pattern or default if no valid input.

Variable Tracker

Variable	Start	Step 1	Step 2	Step 3	Step 4	Step 5	Step 6
in	----	0001	0010	0100	1000	0000	0011
out	00	00	01	10	11	00	00

Key Moments - 3 Insights

What happens if more than one input bit is high at the same time?

The encoder outputs the default value (00) as shown in step 6 of the execution_table because it only encodes single active inputs.

Why does the output default to 00 when no input is high?

Because the default case in the case statement sets output to 00, ensuring a known output even if no inputs are active (step 5).

How does the encoder decide which output to produce?

It checks each input pattern in order using the case statement and assigns the corresponding binary code when a match is found (steps 1 to 4).

Visual Quiz - 3 Questions

Look at the execution_table, what is the output when input is 0100?

A 10

B 01

C 00

D 11

💡 Hint

Check row 3 in the execution_table where input is 0100 and output is assigned.

At which step does the encoder output the default value because no input is high?

A Step 4

B Step 5

C Step 6

D Step 1

💡 Hint

Look for the step where input is 0000 and output is default 00 in the execution_table.

If input is 0011 (two bits high), what output does the encoder produce?

A 01

B 10

C 00

D 11

💡 Hint

Refer to step 6 in the execution_table where multiple inputs are high and output is default 00.

Concept Snapshot

Encoder design in Verilog:
- Input: multiple lines, only one active at a time
- Output: binary code representing active input
- Use case statement to check inputs
- Default output for no or multiple active inputs
- Simple 4-to-2 encoder example shown

Full Transcript

This visual execution trace shows how a 4-to-2 encoder in Verilog works. The encoder checks which single input line is high and outputs a 2-bit binary code representing that input. The case statement matches the input pattern and assigns the output accordingly. If no input or multiple inputs are high, the encoder outputs a default value of 00. The execution table traces inputs and outputs step-by-step, and the variable tracker shows how inputs and outputs change. Key moments clarify common confusions about multiple inputs and default outputs. The quiz tests understanding of output values for given inputs.

Practice

1.

What is the primary function of an encoder in digital design?

easy

A. Store multiple bits of data temporarily

B. Convert binary code into decimal numbers

C. Amplify the input signal strength

D. Convert one active input line into a binary code output

Solution

1. Step 1: Understand the role of an encoder

   An encoder takes multiple input lines but only one is active at a time and converts that active input into a binary code output.

2. Step 2: Compare options with the definition

   Convert one active input line into a binary code output matches the definition exactly, while others describe different components or functions.

3. Final Answer:

   Convert one active input line into a binary code output -> Option D

4. Quick Check:

   Encoder function = binary code output from active input [OK]

Hint: Remember: Encoder outputs binary code for one active input [OK]

Common Mistakes:

• Confusing encoder with decoder
• Thinking encoder stores data
• Assuming encoder amplifies signals

2.

Which of the following is the correct Verilog syntax to start a casez statement for a 4-input encoder?

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    casez(____)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
    endcase
  end
endmodule

easy

A. out

B. in

C. in[3:0]

D. out[1:0]

Solution

1. Step 1: Identify the signal to check in the casez

   The casez statement should check the input signals to decide the output.

2. Step 2: Match the input vector name

   The input vector is named 'in', so casez(in) is correct syntax.

3. Final Answer:

   in -> Option B

4. Quick Check:

   casez checks input vector 'in' [OK]

Hint: Use input signal name inside casez parentheses [OK]

Common Mistakes:

• Using output signal in casez
• Using bit slices incorrectly
• Confusing input and output signals

3.

Given this Verilog snippet for a 4-to-2 encoder, what is the output out when in = 4'b0100?

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    casez(in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'bxx;
    endcase
  end
endmodule

medium

A. 2'b10

B. 2'b01

C. 2'b00

D. 2'b11

Solution

1. Step 1: Match input pattern to casez branches

   The input is 4'b0100, which matches the third case in the casez statement.

2. Step 2: Identify output for matched case

   For 4'b0100, the output is assigned 2'b10.

3. Final Answer:

   2'b10 -> Option A

4. Quick Check:

   Input 0100 maps to output 10 [OK]

Hint: Match input bits exactly to casez patterns [OK]

Common Mistakes:

• Confusing input bit positions
• Choosing default output incorrectly
• Misreading binary literals

4.

Identify the error in this Verilog encoder code snippet:

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    case(in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'bxx;
    endcase
  end
endmodule

What is the main problem?

medium

A. Output out should be declared as wire, not reg

B. Input in should be 2 bits, not 4 bits

C. Using case instead of casez causes incorrect matching with 'x' or 'z'

D. Missing sensitivity list in always block

Solution

1. Step 1: Understand difference between case and casez

   The case statement matches exact bits, but casez allows 'z' and 'x' as wildcards, useful in encoders.

2. Step 2: Identify why casez is preferred here

   Using case can cause mismatches if inputs have unknown bits; casez handles this gracefully.

3. Final Answer:

   Using case instead of casez causes incorrect matching with 'x' or 'z' -> Option C

4. Quick Check:

   Use casez for wildcard matching in encoders [OK]

Hint: Use casez to handle unknown bits in inputs [OK]

Common Mistakes:

• Confusing reg and wire for outputs
• Wrong input width
• Forgetting sensitivity list (@(*) is correct here)

5.

You want to design a 8-to-3 priority encoder in Verilog that outputs the binary code of the highest priority active input. Which approach is best to implement this?

hard

A. Use a casez statement with input patterns ordered from highest to lowest priority

B. Use multiple if statements checking inputs from lowest to highest priority

C. Use a for loop to assign output based on input index without priority checks

D. Use a case statement with unordered input patterns

Solution

1. Step 1: Understand priority encoder requirements

   A priority encoder outputs the code of the highest priority active input among many inputs.

2. Step 2: Choose method to implement priority

   Using casez with patterns ordered from highest to lowest priority ensures the first matched input is the highest priority.

3. Final Answer:

   Use a casez statement with input patterns ordered from highest to lowest priority -> Option A

4. Quick Check:

   Priority encoder needs ordered casez for correct output [OK]

Hint: Order casez patterns by priority for correct encoding [OK]

Common Mistakes:

• Checking inputs in wrong priority order
• Using unordered case statements
• Ignoring priority in loops