Encoder design in Verilog - Mini Project: Build & Apply

Encoder Design in Verilog

📖 Scenario: You are designing a simple digital encoder circuit. An encoder takes multiple input lines and converts them into a binary code on the output lines. This is useful in electronics to reduce the number of wires needed to represent multiple signals.

🎯 Goal: Build a 4-to-2 priority encoder in Verilog. The encoder will take 4 input bits and output a 2-bit binary code representing the highest priority active input.

📋 What You'll Learn

Create a 4-bit input vector called in

Create a 2-bit output vector called out

Create a 1-bit output called valid to indicate if any input is active

Implement priority encoding logic where in[3] has the highest priority and in[0] the lowest

Print the output values in simulation

💡 Why This Matters

🌍 Real World

Encoders are used in digital electronics to reduce the number of wires needed to represent multiple signals, such as in keyboards, multiplexers, and communication systems.

💼 Career

Understanding encoder design is important for hardware engineers and FPGA developers who build efficient digital circuits.

1

DATA SETUP: Define inputs and outputs

Create a Verilog module named encoder with a 4-bit input called in, a 2-bit output called out, and a 1-bit output called valid.

Verilog

module encoder(input [3:0] in, output reg [1:0] out, output reg valid);
// Your code here
endmodule

Hint

Define the module and declare inputs and outputs exactly as specified.

2

CONFIGURATION: Initialize outputs

Inside the encoder module, add an always block that triggers on any change of in. Inside it, initialize out to 0 and valid to 0.

Verilog

module encoder(input [3:0] in, output reg [1:0] out, output reg valid);
    always @ (in) begin
        // Your code here
    end
endmodule

Hint

Use an always block sensitive to in and set out and valid to zero initially.

3

CORE LOGIC: Implement priority encoding

Inside the always block, add if-else statements to check inputs from in[3] down to in[0]. Set out to the binary index of the highest priority active input and valid to 1 if any input is active.

Verilog

module encoder(input [3:0] in, output reg [1:0] out, output reg valid);
    always @ (in) begin
        out = 2'b00;
        valid = 1'b0;
        // Your code here
    end
endmodule

Hint

Check inputs in order from highest to lowest priority and assign out and valid accordingly.

4

OUTPUT: Test the encoder with example inputs

Write a testbench module named test_encoder that instantiates the encoder module. Apply these inputs to in in sequence: 4'b0001, 4'b0010, 4'b0100, 4'b1000, and 4'b0000. Use $display to print in, out, and valid after each input change.

Verilog

module encoder(input [3:0] in, output reg [1:0] out, output reg valid);
    always @ (in) begin
        out = 2'b00;
        valid = 1'b0;
        if (in[3]) begin
            out = 2'b11;
            valid = 1'b1;
        end else if (in[2]) begin
            out = 2'b10;
            valid = 1'b1;
        end else if (in[1]) begin
            out = 2'b01;
            valid = 1'b1;
        end else if (in[0]) begin
            out = 2'b00;
            valid = 1'b1;
        end
    end
endmodule

// Your code here

Hint

Create a testbench that applies inputs and prints the outputs using $display.

Practice

1.

What is the primary function of an encoder in digital design?

easy

A. Store multiple bits of data temporarily

B. Convert binary code into decimal numbers

C. Amplify the input signal strength

D. Convert one active input line into a binary code output

Solution

1. Step 1: Understand the role of an encoder

   An encoder takes multiple input lines but only one is active at a time and converts that active input into a binary code output.

2. Step 2: Compare options with the definition

   Convert one active input line into a binary code output matches the definition exactly, while others describe different components or functions.

3. Final Answer:

   Convert one active input line into a binary code output -> Option D

4. Quick Check:

   Encoder function = binary code output from active input [OK]

Hint: Remember: Encoder outputs binary code for one active input [OK]

Common Mistakes:

• Confusing encoder with decoder
• Thinking encoder stores data
• Assuming encoder amplifies signals

2.

Which of the following is the correct Verilog syntax to start a casez statement for a 4-input encoder?

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    casez(____)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
    endcase
  end
endmodule

easy

A. out

B. in

C. in[3:0]

D. out[1:0]

Solution

1. Step 1: Identify the signal to check in the casez

   The casez statement should check the input signals to decide the output.

2. Step 2: Match the input vector name

   The input vector is named 'in', so casez(in) is correct syntax.

3. Final Answer:

   in -> Option B

4. Quick Check:

   casez checks input vector 'in' [OK]

Hint: Use input signal name inside casez parentheses [OK]

Common Mistakes:

• Using output signal in casez
• Using bit slices incorrectly
• Confusing input and output signals

3.

Given this Verilog snippet for a 4-to-2 encoder, what is the output out when in = 4'b0100?

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    casez(in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'bxx;
    endcase
  end
endmodule

medium

A. 2'b10

B. 2'b01

C. 2'b00

D. 2'b11

Solution

1. Step 1: Match input pattern to casez branches

   The input is 4'b0100, which matches the third case in the casez statement.

2. Step 2: Identify output for matched case

   For 4'b0100, the output is assigned 2'b10.

3. Final Answer:

   2'b10 -> Option A

4. Quick Check:

   Input 0100 maps to output 10 [OK]

Hint: Match input bits exactly to casez patterns [OK]

Common Mistakes:

• Confusing input bit positions
• Choosing default output incorrectly
• Misreading binary literals

4.

Identify the error in this Verilog encoder code snippet:

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    case(in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'bxx;
    endcase
  end
endmodule

What is the main problem?

medium

A. Output out should be declared as wire, not reg

B. Input in should be 2 bits, not 4 bits

C. Using case instead of casez causes incorrect matching with 'x' or 'z'

D. Missing sensitivity list in always block

Solution

1. Step 1: Understand difference between case and casez

   The case statement matches exact bits, but casez allows 'z' and 'x' as wildcards, useful in encoders.

2. Step 2: Identify why casez is preferred here

   Using case can cause mismatches if inputs have unknown bits; casez handles this gracefully.

3. Final Answer:

   Using case instead of casez causes incorrect matching with 'x' or 'z' -> Option C

4. Quick Check:

   Use casez for wildcard matching in encoders [OK]

Hint: Use casez to handle unknown bits in inputs [OK]

Common Mistakes:

• Confusing reg and wire for outputs
• Wrong input width
• Forgetting sensitivity list (@(*) is correct here)

5.

You want to design a 8-to-3 priority encoder in Verilog that outputs the binary code of the highest priority active input. Which approach is best to implement this?

hard

A. Use a casez statement with input patterns ordered from highest to lowest priority

B. Use multiple if statements checking inputs from lowest to highest priority

C. Use a for loop to assign output based on input index without priority checks

D. Use a case statement with unordered input patterns

Solution

1. Step 1: Understand priority encoder requirements

   A priority encoder outputs the code of the highest priority active input among many inputs.

2. Step 2: Choose method to implement priority

   Using casez with patterns ordered from highest to lowest priority ensures the first matched input is the highest priority.

3. Final Answer:

   Use a casez statement with input patterns ordered from highest to lowest priority -> Option A

4. Quick Check:

   Priority encoder needs ordered casez for correct output [OK]

Hint: Order casez patterns by priority for correct encoding [OK]

Common Mistakes:

• Checking inputs in wrong priority order
• Using unordered case statements
• Ignoring priority in loops