Encoder design in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the main purpose of an encoder in digital design?

An encoder converts multiple input lines into a smaller number of output lines by encoding the active input into a binary code.

beginner

In a 4-to-2 encoder, how many input and output lines are there?

There are 4 input lines and 2 output lines. The encoder outputs a 2-bit binary code representing which input is active.

intermediate

What is the difference between a priority encoder and a simple encoder?

A priority encoder outputs the binary code of the highest priority active input when multiple inputs are active, while a simple encoder assumes only one input is active at a time.

intermediate

Write a simple Verilog code snippet for a 4-to-2 encoder using if-else statements.

module encoder_4to2(input [3:0] in, output reg [1:0] out); always @(*) begin if (in[3]) out = 2'b11; else if (in[2]) out = 2'b10; else if (in[1]) out = 2'b01; else if (in[0]) out = 2'b00; else out = 2'b00; // default end endmodule

intermediate

Why is it important to handle the case when no input is active in an encoder design?

Because if no input is active, the encoder output may be undefined or incorrect. Handling this case ensures predictable output and avoids errors in the system.

How many output bits does a 8-to-3 encoder have?

A 3

B 8

C 4

D 1

An 8-to-3 encoder converts 8 input lines into 3 output bits representing the binary code of the active input.

What does a priority encoder do when multiple inputs are active?

A Outputs the sum of all active inputs

B Outputs zero

C Outputs the binary code of the highest priority active input

D Outputs the lowest priority active input

A priority encoder selects the highest priority active input and outputs its binary code.

In Verilog, which block is commonly used to describe combinational logic like an encoder?

A always @(posedge clk)

B always @(*)

C initial

D final

The always @(*) block is used for combinational logic to automatically react to any input changes.

What should an encoder output if no input is active?

A A default or zero code

B Random value

C High impedance

D The last active input code

The encoder should output a default or zero code to avoid undefined behavior.

Which of these is NOT a typical use of an encoder?

A Reducing multiple signals to fewer bits

B Simplifying signal routing

C Generating binary codes from inputs

D Converting analog signals to digital

Converting analog signals to digital is done by ADCs, not encoders.

Explain how a 4-to-2 encoder works and write a simple Verilog code example.

Think about how each input corresponds to a binary output and how to check inputs in order.

Describe the difference between a simple encoder and a priority encoder and why priority is important.

Consider what happens if more than one input is active at the same time.

Practice

1.

What is the primary function of an encoder in digital design?

easy

A. Store multiple bits of data temporarily

B. Convert binary code into decimal numbers

C. Amplify the input signal strength

D. Convert one active input line into a binary code output

Solution

1. Step 1: Understand the role of an encoder

   An encoder takes multiple input lines but only one is active at a time and converts that active input into a binary code output.

2. Step 2: Compare options with the definition

   Convert one active input line into a binary code output matches the definition exactly, while others describe different components or functions.

3. Final Answer:

   Convert one active input line into a binary code output -> Option D

4. Quick Check:

   Encoder function = binary code output from active input [OK]

Hint: Remember: Encoder outputs binary code for one active input [OK]

Common Mistakes:

• Confusing encoder with decoder
• Thinking encoder stores data
• Assuming encoder amplifies signals

2.

Which of the following is the correct Verilog syntax to start a casez statement for a 4-input encoder?

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    casez(____)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
    endcase
  end
endmodule

easy

A. out

B. in

C. in[3:0]

D. out[1:0]

Solution

1. Step 1: Identify the signal to check in the casez

   The casez statement should check the input signals to decide the output.

2. Step 2: Match the input vector name

   The input vector is named 'in', so casez(in) is correct syntax.

3. Final Answer:

   in -> Option B

4. Quick Check:

   casez checks input vector 'in' [OK]

Hint: Use input signal name inside casez parentheses [OK]

Common Mistakes:

• Using output signal in casez
• Using bit slices incorrectly
• Confusing input and output signals

3.

Given this Verilog snippet for a 4-to-2 encoder, what is the output out when in = 4'b0100?

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    casez(in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'bxx;
    endcase
  end
endmodule

medium

A. 2'b10

B. 2'b01

C. 2'b00

D. 2'b11

Solution

1. Step 1: Match input pattern to casez branches

   The input is 4'b0100, which matches the third case in the casez statement.

2. Step 2: Identify output for matched case

   For 4'b0100, the output is assigned 2'b10.

3. Final Answer:

   2'b10 -> Option A

4. Quick Check:

   Input 0100 maps to output 10 [OK]

Hint: Match input bits exactly to casez patterns [OK]

Common Mistakes:

• Confusing input bit positions
• Choosing default output incorrectly
• Misreading binary literals

4.

Identify the error in this Verilog encoder code snippet:

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    case(in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'bxx;
    endcase
  end
endmodule

What is the main problem?

medium

A. Output out should be declared as wire, not reg

B. Input in should be 2 bits, not 4 bits

C. Using case instead of casez causes incorrect matching with 'x' or 'z'

D. Missing sensitivity list in always block

Solution

1. Step 1: Understand difference between case and casez

   The case statement matches exact bits, but casez allows 'z' and 'x' as wildcards, useful in encoders.

2. Step 2: Identify why casez is preferred here

   Using case can cause mismatches if inputs have unknown bits; casez handles this gracefully.

3. Final Answer:

   Using case instead of casez causes incorrect matching with 'x' or 'z' -> Option C

4. Quick Check:

   Use casez for wildcard matching in encoders [OK]

Hint: Use casez to handle unknown bits in inputs [OK]

Common Mistakes:

• Confusing reg and wire for outputs
• Wrong input width
• Forgetting sensitivity list (@(*) is correct here)

5.

You want to design a 8-to-3 priority encoder in Verilog that outputs the binary code of the highest priority active input. Which approach is best to implement this?

hard

A. Use a casez statement with input patterns ordered from highest to lowest priority

B. Use multiple if statements checking inputs from lowest to highest priority

C. Use a for loop to assign output based on input index without priority checks

D. Use a case statement with unordered input patterns

Solution

1. Step 1: Understand priority encoder requirements

   A priority encoder outputs the code of the highest priority active input among many inputs.

2. Step 2: Choose method to implement priority

   Using casez with patterns ordered from highest to lowest priority ensures the first matched input is the highest priority.

3. Final Answer:

   Use a casez statement with input patterns ordered from highest to lowest priority -> Option A

4. Quick Check:

   Priority encoder needs ordered casez for correct output [OK]

Hint: Order casez patterns by priority for correct encoding [OK]

Common Mistakes:

• Checking inputs in wrong priority order
• Using unordered case statements
• Ignoring priority in loops