Encoder design in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-to-2 encoder module with inputs and outputs.

Verilog

module encoder_4to2(input [3:0] [1], output reg [1:0] y);
endmodule

Drag options to blanks, or click blank then click option'

Adata

Bin

Cinput

Dout

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'input' as a variable name causes syntax errors.

Naming the input 'out' confuses input and output.

The input vector is named data to represent the 4 input lines.

2fill in blank

medium

Complete the code to start the always block triggered by input changes.

Verilog

always @([1]) begin
  // encoding logic
end

Drag options to blanks, or click blank then click option'

Aposedge data

B*

Cdata

Dnegedge data

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge or negedge triggers for combinational logic.

Triggering only on 'data' without * causes incomplete sensitivity.

The * means the always block triggers on any change of inputs.

3fill in blank

hard

Fix the error in the case statement selector to use the input vector.

Verilog

case([1])
  4'b0001: y = 2'b00;
  4'b0010: y = 2'b01;
  4'b0100: y = 2'b10;
  4'b1000: y = 2'b11;
  default: y = 2'b00;
endcase

Drag options to blanks, or click blank then click option'

Ainput

By

Cdata

Dout

Attempts:

3 left

💡 Hint

Common Mistakes

Using output variable in case selector.

Using undefined variable names.

The case selector must be the input vector data to encode the input lines.

4fill in blank

hard

Fill both blanks to complete the module declaration and output port type.

Verilog

module encoder_4to2([1] [3:0] data, [2] [1:0] y);
endmodule

Drag options to blanks, or click blank then click option'

Ainput

Boutput reg

Coutput wire

Dinout

Attempts:

3 left

💡 Hint

Common Mistakes

Declaring output as wire when assigned in always block.

Using inout incorrectly.

The input port uses input and the output port uses output reg because y is assigned inside an always block.

5fill in blank

hard

Fill all three blanks to complete the encoding logic with priority if multiple inputs are active.

Verilog

always @(*) begin
  if (data[0]) y = [1];
  else if (data[1]) y = [2];
  else if (data[2]) y = [3];
  else y = 2'b11;
end

Drag options to blanks, or click blank then click option'

A2'b00

B2'b01

C2'b10

D2'b11

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing output codes for input bits.

Not handling priority correctly.

The encoder outputs the binary code of the first active input bit with priority from bit 0 to bit 3.

Practice

1.

What is the primary function of an encoder in digital design?

easy

A. Store multiple bits of data temporarily

B. Convert binary code into decimal numbers

C. Amplify the input signal strength

D. Convert one active input line into a binary code output

Solution

1. Step 1: Understand the role of an encoder

   An encoder takes multiple input lines but only one is active at a time and converts that active input into a binary code output.

2. Step 2: Compare options with the definition

   Convert one active input line into a binary code output matches the definition exactly, while others describe different components or functions.

3. Final Answer:

   Convert one active input line into a binary code output -> Option D

4. Quick Check:

   Encoder function = binary code output from active input [OK]

Hint: Remember: Encoder outputs binary code for one active input [OK]

Common Mistakes:

• Confusing encoder with decoder
• Thinking encoder stores data
• Assuming encoder amplifies signals

2.

Which of the following is the correct Verilog syntax to start a casez statement for a 4-input encoder?

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    casez(____)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
    endcase
  end
endmodule

easy

A. out

B. in

C. in[3:0]

D. out[1:0]

Solution

1. Step 1: Identify the signal to check in the casez

   The casez statement should check the input signals to decide the output.

2. Step 2: Match the input vector name

   The input vector is named 'in', so casez(in) is correct syntax.

3. Final Answer:

   in -> Option B

4. Quick Check:

   casez checks input vector 'in' [OK]

Hint: Use input signal name inside casez parentheses [OK]

Common Mistakes:

• Using output signal in casez
• Using bit slices incorrectly
• Confusing input and output signals

3.

Given this Verilog snippet for a 4-to-2 encoder, what is the output out when in = 4'b0100?

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    casez(in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'bxx;
    endcase
  end
endmodule

medium

A. 2'b10

B. 2'b01

C. 2'b00

D. 2'b11

Solution

1. Step 1: Match input pattern to casez branches

   The input is 4'b0100, which matches the third case in the casez statement.

2. Step 2: Identify output for matched case

   For 4'b0100, the output is assigned 2'b10.

3. Final Answer:

   2'b10 -> Option A

4. Quick Check:

   Input 0100 maps to output 10 [OK]

Hint: Match input bits exactly to casez patterns [OK]

Common Mistakes:

• Confusing input bit positions
• Choosing default output incorrectly
• Misreading binary literals

4.

Identify the error in this Verilog encoder code snippet:

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    case(in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'bxx;
    endcase
  end
endmodule

What is the main problem?

medium

A. Output out should be declared as wire, not reg

B. Input in should be 2 bits, not 4 bits

C. Using case instead of casez causes incorrect matching with 'x' or 'z'

D. Missing sensitivity list in always block

Solution

1. Step 1: Understand difference between case and casez

   The case statement matches exact bits, but casez allows 'z' and 'x' as wildcards, useful in encoders.

2. Step 2: Identify why casez is preferred here

   Using case can cause mismatches if inputs have unknown bits; casez handles this gracefully.

3. Final Answer:

   Using case instead of casez causes incorrect matching with 'x' or 'z' -> Option C

4. Quick Check:

   Use casez for wildcard matching in encoders [OK]

Hint: Use casez to handle unknown bits in inputs [OK]

Common Mistakes:

• Confusing reg and wire for outputs
• Wrong input width
• Forgetting sensitivity list (@(*) is correct here)

5.

You want to design a 8-to-3 priority encoder in Verilog that outputs the binary code of the highest priority active input. Which approach is best to implement this?

hard

A. Use a casez statement with input patterns ordered from highest to lowest priority

B. Use multiple if statements checking inputs from lowest to highest priority

C. Use a for loop to assign output based on input index without priority checks

D. Use a case statement with unordered input patterns

Solution

1. Step 1: Understand priority encoder requirements

   A priority encoder outputs the code of the highest priority active input among many inputs.

2. Step 2: Choose method to implement priority

   Using casez with patterns ordered from highest to lowest priority ensures the first matched input is the highest priority.

3. Final Answer:

   Use a casez statement with input patterns ordered from highest to lowest priority -> Option A

4. Quick Check:

   Priority encoder needs ordered casez for correct output [OK]

Hint: Order casez patterns by priority for correct encoding [OK]

Common Mistakes:

• Checking inputs in wrong priority order
• Using unordered case statements
• Ignoring priority in loops