Encoder design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this 4-to-2 priority encoder?

Given the following Verilog code for a 4-to-2 priority encoder, what is the output y when the input in is 4'b1010?

Verilog

module priority_encoder_4to2(input [3:0] in, output reg [1:0] y);
  always @(*) begin
    casez(in)
      4'b1???: y = 2'b11;
      4'b01??: y = 2'b10;
      4'b001?: y = 2'b01;
      4'b0001: y = 2'b00;
      default: y = 2'b00;
    endcase
  end
endmodule

A y = 2'b01

B y = 2'b10

C y = 2'b11

D y = 2'b00

💡 Hint

Look at the highest priority bit set to 1 in the input.

The input 4'b1010 has bit 3 and bit 1 set. The highest priority bit is bit 3 (leftmost). According to the casez, 4'b1??? matches and outputs 2'b11.

🧠 Conceptual

intermediate

Which statement about encoders is true?

Select the correct statement about a priority encoder.

A It outputs the binary code of the highest priority active input.

B It outputs the number of active inputs.

C It outputs the sum of all active inputs.

D It outputs the lowest priority active input index.

💡 Hint

Think about what 'priority' means in this context.

A priority encoder outputs the binary code corresponding to the highest priority input line that is active (logic 1).

🔧 Debug

advanced

Find the error in this 8-to-3 encoder code

This Verilog code is intended to implement an 8-to-3 encoder. What error will it cause when synthesized or simulated?

Verilog

module encoder_8to3(input [7:0] in, output reg [2:0] y);
  always @(*) begin
    case(in)
      8'b00000001: y = 3'b000;
      8'b00000010: y = 3'b001;
      8'b00000100: y = 3'b010;
      8'b00001000: y = 3'b011;
      8'b00010000: y = 3'b100;
      8'b00100000: y = 3'b101;
      8'b01000000: y = 3'b110;
      8'b10000000: y = 3'b111;
      default: y = 3'bxxx;
    endcase
  end
endmodule

A It will cause a runtime error due to incomplete case coverage.

B It will output 3'b000 for all inputs.

C It will output correct code for multiple active inputs.

D It will cause a synthesis error due to multiple bits set in input.

💡 Hint

Consider what happens if more than one input bit is high.

The code uses a case statement that matches only when exactly one bit is set. If multiple bits are set, no case matches, and the output is undefined or incorrect. This is not a priority encoder and will cause synthesis issues.

📝 Syntax

advanced

Which option fixes the syntax error in this encoder code?

This Verilog snippet has a syntax error. Which option fixes it?

Verilog

module encoder_4to2(input [3:0] in, output reg [1:0] y);
  always @(*) begin
    if (in[3]) y = 2'b11;
    else if (in[2]) y = 2'b10
    else if (in[1]) y = 2'b01;
    else y = 2'b00;
  end
endmodule

A Remove 'reg' from output declaration

B Add a semicolon after 'y = 2'b10'

C Replace 'always @(*)' with 'always @(in)'

D Change 'else if' to 'elseif'

💡 Hint

Look carefully at the line endings.

The line 'else if (in[2]) y = 2'b10' is missing a semicolon at the end, causing a syntax error.

🚀 Application

expert

How many output bits are needed for a 16-to-n encoder?

You want to design an encoder that takes 16 input lines and outputs the binary code of the active input. How many bits should the output have?

A 4 bits

B 8 bits

C 16 bits

D 5 bits

💡 Hint

Think about how many bits are needed to represent numbers from 0 to 15.

To represent 16 different inputs, you need enough bits to count from 0 to 15, which requires 4 bits.

Practice

1.

What is the primary function of an encoder in digital design?

easy

A. Store multiple bits of data temporarily

B. Convert binary code into decimal numbers

C. Amplify the input signal strength

D. Convert one active input line into a binary code output

Solution

1. Step 1: Understand the role of an encoder

   An encoder takes multiple input lines but only one is active at a time and converts that active input into a binary code output.

2. Step 2: Compare options with the definition

   Convert one active input line into a binary code output matches the definition exactly, while others describe different components or functions.

3. Final Answer:

   Convert one active input line into a binary code output -> Option D

4. Quick Check:

   Encoder function = binary code output from active input [OK]

Hint: Remember: Encoder outputs binary code for one active input [OK]

Common Mistakes:

• Confusing encoder with decoder
• Thinking encoder stores data
• Assuming encoder amplifies signals

2.

Which of the following is the correct Verilog syntax to start a casez statement for a 4-input encoder?

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    casez(____)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
    endcase
  end
endmodule

easy

A. out

B. in

C. in[3:0]

D. out[1:0]

Solution

1. Step 1: Identify the signal to check in the casez

   The casez statement should check the input signals to decide the output.

2. Step 2: Match the input vector name

   The input vector is named 'in', so casez(in) is correct syntax.

3. Final Answer:

   in -> Option B

4. Quick Check:

   casez checks input vector 'in' [OK]

Hint: Use input signal name inside casez parentheses [OK]

Common Mistakes:

• Using output signal in casez
• Using bit slices incorrectly
• Confusing input and output signals

3.

Given this Verilog snippet for a 4-to-2 encoder, what is the output out when in = 4'b0100?

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    casez(in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'bxx;
    endcase
  end
endmodule

medium

A. 2'b10

B. 2'b01

C. 2'b00

D. 2'b11

Solution

1. Step 1: Match input pattern to casez branches

   The input is 4'b0100, which matches the third case in the casez statement.

2. Step 2: Identify output for matched case

   For 4'b0100, the output is assigned 2'b10.

3. Final Answer:

   2'b10 -> Option A

4. Quick Check:

   Input 0100 maps to output 10 [OK]

Hint: Match input bits exactly to casez patterns [OK]

Common Mistakes:

• Confusing input bit positions
• Choosing default output incorrectly
• Misreading binary literals

4.

Identify the error in this Verilog encoder code snippet:

module encoder(input [3:0] in, output reg [1:0] out);
  always @(*) begin
    case(in)
      4'b0001: out = 2'b00;
      4'b0010: out = 2'b01;
      4'b0100: out = 2'b10;
      4'b1000: out = 2'b11;
      default: out = 2'bxx;
    endcase
  end
endmodule

What is the main problem?

medium

A. Output out should be declared as wire, not reg

B. Input in should be 2 bits, not 4 bits

C. Using case instead of casez causes incorrect matching with 'x' or 'z'

D. Missing sensitivity list in always block

Solution

1. Step 1: Understand difference between case and casez

   The case statement matches exact bits, but casez allows 'z' and 'x' as wildcards, useful in encoders.

2. Step 2: Identify why casez is preferred here

   Using case can cause mismatches if inputs have unknown bits; casez handles this gracefully.

3. Final Answer:

   Using case instead of casez causes incorrect matching with 'x' or 'z' -> Option C

4. Quick Check:

   Use casez for wildcard matching in encoders [OK]

Hint: Use casez to handle unknown bits in inputs [OK]

Common Mistakes:

• Confusing reg and wire for outputs
• Wrong input width
• Forgetting sensitivity list (@(*) is correct here)

5.

You want to design a 8-to-3 priority encoder in Verilog that outputs the binary code of the highest priority active input. Which approach is best to implement this?

hard

A. Use a casez statement with input patterns ordered from highest to lowest priority

B. Use multiple if statements checking inputs from lowest to highest priority

C. Use a for loop to assign output based on input index without priority checks

D. Use a case statement with unordered input patterns

Solution

1. Step 1: Understand priority encoder requirements

   A priority encoder outputs the code of the highest priority active input among many inputs.

2. Step 2: Choose method to implement priority

   Using casez with patterns ordered from highest to lowest priority ensures the first matched input is the highest priority.

3. Final Answer:

   Use a casez statement with input patterns ordered from highest to lowest priority -> Option A

4. Quick Check:

   Priority encoder needs ordered casez for correct output [OK]

Hint: Order casez patterns by priority for correct encoding [OK]

Common Mistakes:

• Checking inputs in wrong priority order
• Using unordered case statements
• Ignoring priority in loops