Array declaration in Verilog - Step-by-Step Execution

Concept Flow - Array declaration

Start

↓

Choose data type

↓

Specify element width

↓

Specify array name

↓

Define array size

↓

Use syntax: type [width-1:0

↓

Array declared

↓

End

This flow shows how to declare an array in Verilog by choosing a data type, specifying the element width, naming the array, and specifying its size.

Execution Sample

Verilog

reg [7:0] my_array [0:3];

// Declares an array of 4 elements, each 8 bits wide.

Declares a 4-element array named my_array, each element is 8 bits.

Execution Table

Step	Action	Syntax Used	Array Size	Element Width	Result
1	Choose data type	reg	-	-	Data type set to reg
2	Specify element width	[7:0]	-	8 bits	Each element is 8 bits wide
3	Specify array name	my_array	-	-	Array named my_array
4	Define array size	[0:3]	4 elements	8 bits	Array size set to 4 elements
5	Complete declaration	reg [7:0] my_array [0:3];	4 elements	8 bits	Array declared successfully
6	End	-	-	-	Declaration complete

💡 Array declared with 4 elements, each 8 bits wide, named my_array.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	Final
Data Type	undefined	reg	reg	reg	reg	reg
Element Width	undefined	undefined	8 bits	8 bits	8 bits	8 bits
Array Name	undefined	undefined	undefined	my_array	my_array	my_array
Array Size	undefined	undefined	undefined	undefined	4 elements	4 elements

Key Moments - 3 Insights

Why do we write the element width before the array size in the declaration?

In Verilog, the element width (like [7:0]) specifies the size of each element, and it must come before the array size (like [0:3]) which specifies how many elements. This order is shown in the execution_table rows 2 and 4.

What does [0:3] mean in the array declaration?

It means the array has 4 elements indexed from 0 to 3. This is clarified in execution_table row 4 where array size is set to 4 elements.

Can we declare an array without specifying the element width?

Yes, but without it, the array elements default to 1 bit. The element width defines how many bits each element holds. This is shown in execution_table row 2 where element width is set.

Visual Quiz - 3 Questions

Look at the execution_table, what is the element width after step 2?

A reg

B 4 elements

C 8 bits

D undefined

💡 Hint

Check the 'Element Width' column at step 2 in the execution_table.

At which step is the array size defined?

A Step 1

B Step 4

C Step 3

D Step 5

💡 Hint

Look at the 'Action' column in the execution_table for when array size is set.

If we change the array size to [0:7], how would the 'Array Size' column change in the execution_table?

A It would show 8 elements

B It would show 7 elements

C It would show 0 elements

D It would remain 4 elements

💡 Hint

Array size is the count of elements from the index range, so [0:7] means 8 elements.

Concept Snapshot

Verilog array declaration syntax:
reg [element_width-1:0] array_name [array_size_range];
- 'reg' is data type
- [7:0] means 8-bit elements
- [0:3] means 4 elements indexed 0 to 3
- Declare arrays by specifying element width then size
- Used for grouping multiple data elements

Full Transcript

This visual execution trace shows how to declare an array in Verilog. First, you choose the data type like 'reg'. Then specify the element width, for example [7:0] for 8 bits. Next, you name the array, such as 'my_array'. After that, define the array size with a range like [0:3], which means 4 elements. The full declaration looks like 'reg [7:0] my_array [0:3];'. The execution table walks through each step, showing how variables change. Key moments clarify common confusions like why element width comes before array size and what the index range means. The quiz tests understanding of these steps. This helps beginners see exactly how Verilog arrays are declared step-by-step.

Practice

1. What is the correct way to declare a 16-bit wide array with 8 elements in Verilog?

easy

A. reg [0:7] my_array [15:0];

B. reg my_array [15:0] [0:7];

C. reg [15:0] my_array [0:7];

D. reg [7:0] my_array [0:15];

Solution

1. Step 1: Understand bit width and size syntax

   In Verilog, the bit width is declared first as [bit_width-1:0], so for 16 bits it is [15:0].

2. Step 2: Declare array size correctly

   The array size is declared after the variable name as [0:size-1], so for 8 elements it is [0:7].

3. Final Answer:

   reg [15:0] my_array [0:7]; -> Option C

4. Quick Check:

   Bit width then array size = reg [15:0] my_array [0:7]; [OK]

Hint: Bit width first, then array size in brackets [OK]

Common Mistakes:

• Swapping bit width and array size positions
• Using incorrect bit range like [0:7] for bit width
• Confusing array size with bit width

2. Which of the following is a syntax error when declaring an array in Verilog?

easy

A. reg [7:0] data_array [0:15];

B. reg [7:0] data_array [0:7];

C. reg [0:7] data_array [0:15];

D. reg [7:0] data_array [15:0];

Solution

1. Step 1: Check array size declaration

   Array size must be declared as [start_index:end_index] with start_index less than end_index, usually [0:size-1].

2. Step 2: Identify invalid range

   reg [7:0] data_array [15:0]; uses [15:0], which is reversed and invalid for array indexing.

3. Final Answer:

   reg [7:0] data_array [15:0]; -> Option D

4. Quick Check:

   Array index must be ascending range [OK]

Hint: Array index must go from low to high [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width range with array index range
• Forgetting semicolon at end

3. Given the declaration reg [3:0] arr [0:3]; and the assignments arr[0] = 4'b1010;, arr[1] = 4'b0101;, what is the value of arr[1]?

medium

A. 4'b0101

B. 4'b1111

C. 4'b1010

D. 4'b0000

Solution

1. Step 1: Understand array declaration and assignments

   The array arr has 4 elements indexed 0 to 3, each 4 bits wide. arr[0] is assigned 1010, arr[1] is assigned 0101.

2. Step 2: Identify value of arr[1]

   arr[1] was explicitly assigned 4'b0101, so its value is 0101.

3. Final Answer:

   4'b0101 -> Option A

4. Quick Check:

   arr[1] = 4'b0101 [OK]

Hint: Index matches assigned value directly [OK]

Common Mistakes:

• Mixing up indices and values
• Assuming default zero without assignment
• Confusing bit width with array size

4. Identify the error in the following Verilog array declaration:

reg [7:0] mem_array [7:0];

medium

A. Array size range should be [0:7], not [7:0]

B. Bit width and array size are swapped

C. No error, declaration is correct

D. Missing semicolon at the end

Solution

1. Step 1: Analyze array size range

   The array size is declared as [7:0], which is a descending range and invalid for array indexing.

2. Step 2: Correct array size range

   The correct array size should be ascending, [0:7], to declare 8 elements indexed 0 to 7.

3. Final Answer:

   Array size range should be [0:7], not [7:0] -> Option A

4. Quick Check:

   Array index must be ascending [OK]

Hint: Array index must count up, not down [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width with array size
• Assuming [7:0] is valid for arrays

5. How would you declare a 2-dimensional array in Verilog with 4 rows and 8 columns, each element 8 bits wide?

hard

A. reg [7:0] matrix [0:7][0:3];

B. reg [7:0] matrix [0:3][0:7];

C. reg matrix [7:0][3:0];

D. reg [3:0] matrix [7:0];

Solution

1. Step 1: Understand 2D array declaration syntax

   In Verilog, multi-dimensional arrays are declared by stacking sizes after the variable name. The first dimension is rows, second is columns.

2. Step 2: Apply correct sizes and bit width

   Each element is 8 bits wide, so bit width is [7:0]. Rows are 4 elements indexed 0 to 3, columns are 8 elements indexed 0 to 7.

3. Final Answer:

   reg [7:0] matrix [0:3][0:7]; -> Option B

4. Quick Check:

   Bit width then rows then columns [OK]

Hint: Declare bit width first, then each dimension [OK]

Common Mistakes:

• Swapping row and column indices
• Incorrect bit width declaration
• Using reversed index ranges