Array declaration in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog array declaration?

Consider the following Verilog code snippet. What is the width and number of elements of the declared array?

Verilog

reg [7:0] my_array [0:3];

A An array of 0 elements, each 8 bits wide

B An array of 8 elements, each 4 bits wide

C An array of 3 elements, each 7 bits wide

D An array of 4 elements, each 8 bits wide

💡 Hint

Look at the range in the declaration and the bit width inside the brackets.

The declaration reg [7:0] my_array [0:3]; creates an array with indices from 0 to 3, so 4 elements total. Each element is 8 bits wide (from 7 down to 0).

❓ Predict Output

intermediate

What is the size of this multidimensional array?

Given this Verilog declaration, how many total bits does the array occupy?

Verilog

reg [3:0] matrix [0:1][0:2];

A 24 bits total

B 12 bits total

C 6 bits total

D 8 bits total

💡 Hint

Multiply the number of elements in each dimension by the bit width.

The array has 2 elements in the first dimension (0 to 1) and 3 in the second (0 to 2), total 6 elements. Each element is 4 bits wide, so 6 * 4 = 24 bits total.

🔧 Debug

advanced

Identify the error in this array declaration

What error will this Verilog code produce?

Verilog

reg [7:0] data_array [7];

A No error, valid declaration

B SyntaxError: Missing range for array indices

C TypeError: Invalid bit width

D RuntimeError: Array size too large

💡 Hint

Array indices must specify a range, not a single number.

In Verilog, array declarations require a range for indices like [0:7], not a single number [7]. Using [7] alone is a syntax error.

❓ Predict Output

advanced

What is the value of element after assignment?

Given this Verilog code, what is the value of my_array[2] after execution?

Verilog

reg [3:0] my_array [0:3];
initial begin
  my_array[2] = 4'b1010;
end

A 4'b1010

B 4'b0101

C 4'b1111

D 4'b0000

💡 Hint

Look at the assignment statement carefully.

The code assigns the binary value 1010 to my_array[2], so its value is 4'b1010.

🧠 Conceptual

expert

How does Verilog store packed vs unpacked arrays?

Which statement correctly describes the difference between packed and unpacked arrays in Verilog?

A There is no difference; both store data the same way.

B Unpacked arrays store bits contiguously and can be sliced; packed arrays are arrays of variables stored separately.

C Packed arrays store bits contiguously and can be sliced; unpacked arrays are arrays of variables stored separately.

D Packed arrays are only for integers; unpacked arrays are only for registers.

💡 Hint

Think about how bits are arranged and accessed in memory.

Packed arrays are stored as contiguous bits and support slicing like vectors. Unpacked arrays are arrays of separate variables and do not support slicing.

Practice

1. What is the correct way to declare a 16-bit wide array with 8 elements in Verilog?

easy

A. reg [0:7] my_array [15:0];

B. reg my_array [15:0] [0:7];

C. reg [15:0] my_array [0:7];

D. reg [7:0] my_array [0:15];

Solution

1. Step 1: Understand bit width and size syntax

   In Verilog, the bit width is declared first as [bit_width-1:0], so for 16 bits it is [15:0].

2. Step 2: Declare array size correctly

   The array size is declared after the variable name as [0:size-1], so for 8 elements it is [0:7].

3. Final Answer:

   reg [15:0] my_array [0:7]; -> Option C

4. Quick Check:

   Bit width then array size = reg [15:0] my_array [0:7]; [OK]

Hint: Bit width first, then array size in brackets [OK]

Common Mistakes:

• Swapping bit width and array size positions
• Using incorrect bit range like [0:7] for bit width
• Confusing array size with bit width

2. Which of the following is a syntax error when declaring an array in Verilog?

easy

A. reg [7:0] data_array [0:15];

B. reg [7:0] data_array [0:7];

C. reg [0:7] data_array [0:15];

D. reg [7:0] data_array [15:0];

Solution

1. Step 1: Check array size declaration

   Array size must be declared as [start_index:end_index] with start_index less than end_index, usually [0:size-1].

2. Step 2: Identify invalid range

   reg [7:0] data_array [15:0]; uses [15:0], which is reversed and invalid for array indexing.

3. Final Answer:

   reg [7:0] data_array [15:0]; -> Option D

4. Quick Check:

   Array index must be ascending range [OK]

Hint: Array index must go from low to high [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width range with array index range
• Forgetting semicolon at end

3. Given the declaration reg [3:0] arr [0:3]; and the assignments arr[0] = 4'b1010;, arr[1] = 4'b0101;, what is the value of arr[1]?

medium

A. 4'b0101

B. 4'b1111

C. 4'b1010

D. 4'b0000

Solution

1. Step 1: Understand array declaration and assignments

   The array arr has 4 elements indexed 0 to 3, each 4 bits wide. arr[0] is assigned 1010, arr[1] is assigned 0101.

2. Step 2: Identify value of arr[1]

   arr[1] was explicitly assigned 4'b0101, so its value is 0101.

3. Final Answer:

   4'b0101 -> Option A

4. Quick Check:

   arr[1] = 4'b0101 [OK]

Hint: Index matches assigned value directly [OK]

Common Mistakes:

• Mixing up indices and values
• Assuming default zero without assignment
• Confusing bit width with array size

4. Identify the error in the following Verilog array declaration:

reg [7:0] mem_array [7:0];

medium

A. Array size range should be [0:7], not [7:0]

B. Bit width and array size are swapped

C. No error, declaration is correct

D. Missing semicolon at the end

Solution

1. Step 1: Analyze array size range

   The array size is declared as [7:0], which is a descending range and invalid for array indexing.

2. Step 2: Correct array size range

   The correct array size should be ascending, [0:7], to declare 8 elements indexed 0 to 7.

3. Final Answer:

   Array size range should be [0:7], not [7:0] -> Option A

4. Quick Check:

   Array index must be ascending [OK]

Hint: Array index must count up, not down [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width with array size
• Assuming [7:0] is valid for arrays

5. How would you declare a 2-dimensional array in Verilog with 4 rows and 8 columns, each element 8 bits wide?

hard

A. reg [7:0] matrix [0:7][0:3];

B. reg [7:0] matrix [0:3][0:7];

C. reg matrix [7:0][3:0];

D. reg [3:0] matrix [7:0];

Solution

1. Step 1: Understand 2D array declaration syntax

   In Verilog, multi-dimensional arrays are declared by stacking sizes after the variable name. The first dimension is rows, second is columns.

2. Step 2: Apply correct sizes and bit width

   Each element is 8 bits wide, so bit width is [7:0]. Rows are 4 elements indexed 0 to 3, columns are 8 elements indexed 0 to 7.

3. Final Answer:

   reg [7:0] matrix [0:3][0:7]; -> Option B

4. Quick Check:

   Bit width then rows then columns [OK]

Hint: Declare bit width first, then each dimension [OK]

Common Mistakes:

• Swapping row and column indices
• Incorrect bit width declaration
• Using reversed index ranges