Array declaration in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the basic syntax to declare a one-dimensional array in Verilog?

In Verilog, a one-dimensional array is declared using the syntax:
reg [bit_width-1:0] array_name [array_size-1:0];
For example, reg [7:0] my_array [0:15]; declares an array of 16 elements, each 8 bits wide.

intermediate

How do you declare a two-dimensional array in Verilog?

You declare a two-dimensional array by specifying two ranges: one for the bit width and one for the number of elements in each dimension.
Example:
reg [7:0] matrix [0:3][0:3];
This creates a 4x4 array where each element is 8 bits wide.

intermediate

What is the difference between reg [7:0] arr [0:15]; and reg arr [0:15][7:0]; in Verilog?

The first declares an array of 16 elements, each 8 bits wide (bit width first).
The second is invalid syntax in Verilog because the bit width must be declared before the array size.
Verilog requires the bit width to be declared as a range before the array dimensions.

beginner

Can you declare an array of wires in Verilog? How?

Yes, you can declare an array of wires using:
wire [bit_width-1:0] wire_array [array_size-1:0];
For example:
wire [3:0] bus_array [0:7]; declares 8 wires, each 4 bits wide.

beginner

What happens if you declare an array without specifying the bit width in Verilog?

If you declare an array without bit width, like reg array [0:7];, each element defaults to 1 bit wide.
This means each element is a single bit, not a vector.

How do you declare a 16-element array of 8-bit registers in Verilog?

A reg [7:0] my_array [0:15];

B reg my_array [0:15][7:0];

C reg [15:0] my_array [0:7];

D wire [7:0] my_array [0:15];

Option A correctly declares 16 elements (0 to 15), each 8 bits wide. Option B is invalid syntax. Option C reverses sizes. Option D declares wires, not registers.

What is the default bit width of an array element if not specified in Verilog?

A 8 bits

B 32 bits

C 16 bits

D 1 bit

If bit width is not specified, each element defaults to 1 bit wide.

Which of the following declares a 4x4 two-dimensional array of 8-bit registers?

A reg [3:0] matrix [7:0];

B reg matrix [0:3][0:3][7:0];

C reg [7:0] matrix [0:3][0:3];

D wire [7:0] matrix [0:3];

Option C correctly declares a 4x4 array with 8-bit elements. Option B is invalid syntax. Option A reverses bit width and size. Option D declares wires, not registers.

Can you declare an array of wires in Verilog?

A Yes, using wire [bit_width-1:0] array_name [size];

B Yes, but only one-dimensional

C No, only registers can be arrays

D No, wires cannot be grouped

Wires can be declared as arrays with the syntax wire [bit_width-1:0] array_name [size];

What is wrong with this declaration? reg arr [0:7][7:0];

A Nothing, it's correct

B Bit width must be declared before array size

C Array size must be declared before bit width

D Cannot declare multi-dimensional arrays

In Verilog, bit width must be declared before array size. This declaration reverses the order.

Explain how to declare a one-dimensional array of 8-bit registers with 16 elements in Verilog.

Remember bit width comes before array size.

Describe the difference between declaring arrays of wires and arrays of registers in Verilog.

Think about how wires and registers behave in hardware.

Practice

1. What is the correct way to declare a 16-bit wide array with 8 elements in Verilog?

easy

A. reg [0:7] my_array [15:0];

B. reg my_array [15:0] [0:7];

C. reg [15:0] my_array [0:7];

D. reg [7:0] my_array [0:15];

Solution

1. Step 1: Understand bit width and size syntax

   In Verilog, the bit width is declared first as [bit_width-1:0], so for 16 bits it is [15:0].

2. Step 2: Declare array size correctly

   The array size is declared after the variable name as [0:size-1], so for 8 elements it is [0:7].

3. Final Answer:

   reg [15:0] my_array [0:7]; -> Option C

4. Quick Check:

   Bit width then array size = reg [15:0] my_array [0:7]; [OK]

Hint: Bit width first, then array size in brackets [OK]

Common Mistakes:

• Swapping bit width and array size positions
• Using incorrect bit range like [0:7] for bit width
• Confusing array size with bit width

2. Which of the following is a syntax error when declaring an array in Verilog?

easy

A. reg [7:0] data_array [0:15];

B. reg [7:0] data_array [0:7];

C. reg [0:7] data_array [0:15];

D. reg [7:0] data_array [15:0];

Solution

1. Step 1: Check array size declaration

   Array size must be declared as [start_index:end_index] with start_index less than end_index, usually [0:size-1].

2. Step 2: Identify invalid range

   reg [7:0] data_array [15:0]; uses [15:0], which is reversed and invalid for array indexing.

3. Final Answer:

   reg [7:0] data_array [15:0]; -> Option D

4. Quick Check:

   Array index must be ascending range [OK]

Hint: Array index must go from low to high [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width range with array index range
• Forgetting semicolon at end

3. Given the declaration reg [3:0] arr [0:3]; and the assignments arr[0] = 4'b1010;, arr[1] = 4'b0101;, what is the value of arr[1]?

medium

A. 4'b0101

B. 4'b1111

C. 4'b1010

D. 4'b0000

Solution

1. Step 1: Understand array declaration and assignments

   The array arr has 4 elements indexed 0 to 3, each 4 bits wide. arr[0] is assigned 1010, arr[1] is assigned 0101.

2. Step 2: Identify value of arr[1]

   arr[1] was explicitly assigned 4'b0101, so its value is 0101.

3. Final Answer:

   4'b0101 -> Option A

4. Quick Check:

   arr[1] = 4'b0101 [OK]

Hint: Index matches assigned value directly [OK]

Common Mistakes:

• Mixing up indices and values
• Assuming default zero without assignment
• Confusing bit width with array size

4. Identify the error in the following Verilog array declaration:

reg [7:0] mem_array [7:0];

medium

A. Array size range should be [0:7], not [7:0]

B. Bit width and array size are swapped

C. No error, declaration is correct

D. Missing semicolon at the end

Solution

1. Step 1: Analyze array size range

   The array size is declared as [7:0], which is a descending range and invalid for array indexing.

2. Step 2: Correct array size range

   The correct array size should be ascending, [0:7], to declare 8 elements indexed 0 to 7.

3. Final Answer:

   Array size range should be [0:7], not [7:0] -> Option A

4. Quick Check:

   Array index must be ascending [OK]

Hint: Array index must count up, not down [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width with array size
• Assuming [7:0] is valid for arrays

5. How would you declare a 2-dimensional array in Verilog with 4 rows and 8 columns, each element 8 bits wide?

hard

A. reg [7:0] matrix [0:7][0:3];

B. reg [7:0] matrix [0:3][0:7];

C. reg matrix [7:0][3:0];

D. reg [3:0] matrix [7:0];

Solution

1. Step 1: Understand 2D array declaration syntax

   In Verilog, multi-dimensional arrays are declared by stacking sizes after the variable name. The first dimension is rows, second is columns.

2. Step 2: Apply correct sizes and bit width

   Each element is 8 bits wide, so bit width is [7:0]. Rows are 4 elements indexed 0 to 3, columns are 8 elements indexed 0 to 7.

3. Final Answer:

   reg [7:0] matrix [0:3][0:7]; -> Option B

4. Quick Check:

   Bit width then rows then columns [OK]

Hint: Declare bit width first, then each dimension [OK]

Common Mistakes:

• Swapping row and column indices
• Incorrect bit width declaration
• Using reversed index ranges