Array declaration in Verilog - Mini Project: Build & Apply

Array declaration

📖 Scenario: You are designing a simple digital system that needs to store multiple 8-bit values. Arrays in Verilog help you organize these values efficiently.

🎯 Goal: Create and use an array in Verilog to hold 4 elements, each 8 bits wide.

📋 What You'll Learn

Declare a 4-element array of 8-bit registers named data_array.

Create a variable index to select an element.

Assign a value to one element of the array using index.

Display the value of the selected array element.

💡 Why This Matters

🌍 Real World

Arrays in Verilog are used to store multiple values like sensor readings or configuration data in hardware designs.

💼 Career

Understanding array declaration and usage is essential for hardware engineers working on FPGA or ASIC designs.

1

Declare a 4-element 8-bit array

Declare a register array called data_array with 4 elements, each 8 bits wide.

Verilog

// Declare the array data_array here
// Your code here

Hint

Use reg [7:0] data_array [0:3]; to declare an array of 4 elements, each 8 bits.

2

Create an index variable

Declare a register variable called index that can hold values from 0 to 3.

Verilog

reg [7:0] data_array [0:3];
// Declare the index variable here
// Your code here

Hint

Use reg [1:0] index; because 2 bits can represent 0 to 3.

3

Assign a value to an array element

Assign the value 8'hA5 to the element of data_array at position index.

Verilog

reg [7:0] data_array [0:3];
reg [1:0] index;
// Assign 8'hA5 to data_array at index
// Your code here

Hint

Set index to 2 (binary 10) and assign 8'hA5 to data_array[index].

4

Display the value of the selected array element

Use $display to print the value of data_array[index].

Verilog

reg [7:0] data_array [0:3];
reg [1:0] index;

initial begin
    index = 2'b10;
    data_array[index] = 8'hA5;
    // Display the value of data_array at index
    // Your code here
end

Hint

Use $display("Value at data_array[%0d] = %h", index, data_array[index]); to print the value.

Practice

1. What is the correct way to declare a 16-bit wide array with 8 elements in Verilog?

easy

A. reg [0:7] my_array [15:0];

B. reg my_array [15:0] [0:7];

C. reg [15:0] my_array [0:7];

D. reg [7:0] my_array [0:15];

Solution

1. Step 1: Understand bit width and size syntax

   In Verilog, the bit width is declared first as [bit_width-1:0], so for 16 bits it is [15:0].

2. Step 2: Declare array size correctly

   The array size is declared after the variable name as [0:size-1], so for 8 elements it is [0:7].

3. Final Answer:

   reg [15:0] my_array [0:7]; -> Option C

4. Quick Check:

   Bit width then array size = reg [15:0] my_array [0:7]; [OK]

Hint: Bit width first, then array size in brackets [OK]

Common Mistakes:

• Swapping bit width and array size positions
• Using incorrect bit range like [0:7] for bit width
• Confusing array size with bit width

2. Which of the following is a syntax error when declaring an array in Verilog?

easy

A. reg [7:0] data_array [0:15];

B. reg [7:0] data_array [0:7];

C. reg [0:7] data_array [0:15];

D. reg [7:0] data_array [15:0];

Solution

1. Step 1: Check array size declaration

   Array size must be declared as [start_index:end_index] with start_index less than end_index, usually [0:size-1].

2. Step 2: Identify invalid range

   reg [7:0] data_array [15:0]; uses [15:0], which is reversed and invalid for array indexing.

3. Final Answer:

   reg [7:0] data_array [15:0]; -> Option D

4. Quick Check:

   Array index must be ascending range [OK]

Hint: Array index must go from low to high [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width range with array index range
• Forgetting semicolon at end

3. Given the declaration reg [3:0] arr [0:3]; and the assignments arr[0] = 4'b1010;, arr[1] = 4'b0101;, what is the value of arr[1]?

medium

A. 4'b0101

B. 4'b1111

C. 4'b1010

D. 4'b0000

Solution

1. Step 1: Understand array declaration and assignments

   The array arr has 4 elements indexed 0 to 3, each 4 bits wide. arr[0] is assigned 1010, arr[1] is assigned 0101.

2. Step 2: Identify value of arr[1]

   arr[1] was explicitly assigned 4'b0101, so its value is 0101.

3. Final Answer:

   4'b0101 -> Option A

4. Quick Check:

   arr[1] = 4'b0101 [OK]

Hint: Index matches assigned value directly [OK]

Common Mistakes:

• Mixing up indices and values
• Assuming default zero without assignment
• Confusing bit width with array size

4. Identify the error in the following Verilog array declaration:

reg [7:0] mem_array [7:0];

medium

A. Array size range should be [0:7], not [7:0]

B. Bit width and array size are swapped

C. No error, declaration is correct

D. Missing semicolon at the end

Solution

1. Step 1: Analyze array size range

   The array size is declared as [7:0], which is a descending range and invalid for array indexing.

2. Step 2: Correct array size range

   The correct array size should be ascending, [0:7], to declare 8 elements indexed 0 to 7.

3. Final Answer:

   Array size range should be [0:7], not [7:0] -> Option A

4. Quick Check:

   Array index must be ascending [OK]

Hint: Array index must count up, not down [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width with array size
• Assuming [7:0] is valid for arrays

5. How would you declare a 2-dimensional array in Verilog with 4 rows and 8 columns, each element 8 bits wide?

hard

A. reg [7:0] matrix [0:7][0:3];

B. reg [7:0] matrix [0:3][0:7];

C. reg matrix [7:0][3:0];

D. reg [3:0] matrix [7:0];

Solution

1. Step 1: Understand 2D array declaration syntax

   In Verilog, multi-dimensional arrays are declared by stacking sizes after the variable name. The first dimension is rows, second is columns.

2. Step 2: Apply correct sizes and bit width

   Each element is 8 bits wide, so bit width is [7:0]. Rows are 4 elements indexed 0 to 3, columns are 8 elements indexed 0 to 7.

3. Final Answer:

   reg [7:0] matrix [0:3][0:7]; -> Option B

4. Quick Check:

   Bit width then rows then columns [OK]

Hint: Declare bit width first, then each dimension [OK]

Common Mistakes:

• Swapping row and column indices
• Incorrect bit width declaration
• Using reversed index ranges