Array declaration in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-element array of 8-bit registers.

Verilog

reg [7:0] my_array [0:[1]];

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A8

B4

C7

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 as the last index instead of 3.

Confusing bit width with array size.

The array indices start at 0, so for 4 elements, the last index is 3.

2fill in blank

medium

Complete the code to declare a 16-element array of 1-bit registers.

Verilog

reg [1] my_bits [0:15];

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A7:0

B0

C1

D15:0

Attempts:

3 left

💡 Hint

Common Mistakes

Using [7:0] for a single bit.

Using [15:0] which is a 16-bit vector, not a single bit.

For 1-bit registers, no range is needed or use [0]. Here, '0' means a single bit.

3fill in blank

hard

Fix the error in the array declaration for a 10-element array of 4-bit registers.

Verilog

reg [[1]:0] data_array [0:9];

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A3

B4

C0

D9

Attempts:

3 left

💡 Hint

Common Mistakes

Using [4:0] which is 5 bits instead of 4.

Using [0:3] which is reversed.

The bit range should be from 3 down to 0 for 4 bits.

4fill in blank

hard

Fill both blanks to declare a 2D array with 8 elements each of 16-bit registers.

Verilog

reg [[1]:0] matrix [0:[2]];

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A15

B7

C8

D16

Attempts:

3 left

💡 Hint

Common Mistakes

Using 16 as the upper bit index which is off by one.

Using 8 as the last array index which is off by one.

The bit width is 16 bits, so indices go from 15 down to 0. The array has 8 elements, so indices go from 0 to 7.

5fill in blank

hard

Fill all three blanks to declare a 3D array of 4-bit registers with dimensions 4x4x4.

Verilog

reg [[1]:0] cube [0:[2]][0:[3]];

Drag options to blanks, or click blank then click option'

A3

B4

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 as the upper bit index which is off by one.

Using 4 as the last array index which is off by one.

The bit width is 4 bits, so indices go from 3 down to 0. Each dimension has 4 elements, so indices go from 0 to 3.

Practice

1. What is the correct way to declare a 16-bit wide array with 8 elements in Verilog?

easy

A. reg [0:7] my_array [15:0];

B. reg my_array [15:0] [0:7];

C. reg [15:0] my_array [0:7];

D. reg [7:0] my_array [0:15];

Solution

1. Step 1: Understand bit width and size syntax

   In Verilog, the bit width is declared first as [bit_width-1:0], so for 16 bits it is [15:0].

2. Step 2: Declare array size correctly

   The array size is declared after the variable name as [0:size-1], so for 8 elements it is [0:7].

3. Final Answer:

   reg [15:0] my_array [0:7]; -> Option C

4. Quick Check:

   Bit width then array size = reg [15:0] my_array [0:7]; [OK]

Hint: Bit width first, then array size in brackets [OK]

Common Mistakes:

• Swapping bit width and array size positions
• Using incorrect bit range like [0:7] for bit width
• Confusing array size with bit width

2. Which of the following is a syntax error when declaring an array in Verilog?

easy

A. reg [7:0] data_array [0:15];

B. reg [7:0] data_array [0:7];

C. reg [0:7] data_array [0:15];

D. reg [7:0] data_array [15:0];

Solution

1. Step 1: Check array size declaration

   Array size must be declared as [start_index:end_index] with start_index less than end_index, usually [0:size-1].

2. Step 2: Identify invalid range

   reg [7:0] data_array [15:0]; uses [15:0], which is reversed and invalid for array indexing.

3. Final Answer:

   reg [7:0] data_array [15:0]; -> Option D

4. Quick Check:

   Array index must be ascending range [OK]

Hint: Array index must go from low to high [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width range with array index range
• Forgetting semicolon at end

3. Given the declaration reg [3:0] arr [0:3]; and the assignments arr[0] = 4'b1010;, arr[1] = 4'b0101;, what is the value of arr[1]?

medium

A. 4'b0101

B. 4'b1111

C. 4'b1010

D. 4'b0000

Solution

1. Step 1: Understand array declaration and assignments

   The array arr has 4 elements indexed 0 to 3, each 4 bits wide. arr[0] is assigned 1010, arr[1] is assigned 0101.

2. Step 2: Identify value of arr[1]

   arr[1] was explicitly assigned 4'b0101, so its value is 0101.

3. Final Answer:

   4'b0101 -> Option A

4. Quick Check:

   arr[1] = 4'b0101 [OK]

Hint: Index matches assigned value directly [OK]

Common Mistakes:

• Mixing up indices and values
• Assuming default zero without assignment
• Confusing bit width with array size

4. Identify the error in the following Verilog array declaration:

reg [7:0] mem_array [7:0];

medium

A. Array size range should be [0:7], not [7:0]

B. Bit width and array size are swapped

C. No error, declaration is correct

D. Missing semicolon at the end

Solution

1. Step 1: Analyze array size range

   The array size is declared as [7:0], which is a descending range and invalid for array indexing.

2. Step 2: Correct array size range

   The correct array size should be ascending, [0:7], to declare 8 elements indexed 0 to 7.

3. Final Answer:

   Array size range should be [0:7], not [7:0] -> Option A

4. Quick Check:

   Array index must be ascending [OK]

Hint: Array index must count up, not down [OK]

Common Mistakes:

• Using descending ranges for array size
• Confusing bit width with array size
• Assuming [7:0] is valid for arrays

5. How would you declare a 2-dimensional array in Verilog with 4 rows and 8 columns, each element 8 bits wide?

hard

A. reg [7:0] matrix [0:7][0:3];

B. reg [7:0] matrix [0:3][0:7];

C. reg matrix [7:0][3:0];

D. reg [3:0] matrix [7:0];

Solution

1. Step 1: Understand 2D array declaration syntax

   In Verilog, multi-dimensional arrays are declared by stacking sizes after the variable name. The first dimension is rows, second is columns.

2. Step 2: Apply correct sizes and bit width

   Each element is 8 bits wide, so bit width is [7:0]. Rows are 4 elements indexed 0 to 3, columns are 8 elements indexed 0 to 7.

3. Final Answer:

   reg [7:0] matrix [0:3][0:7]; -> Option B

4. Quick Check:

   Bit width then rows then columns [OK]

Hint: Declare bit width first, then each dimension [OK]

Common Mistakes:

• Swapping row and column indices
• Incorrect bit width declaration
• Using reversed index ranges