Adder design (half adder, full adder) in Verilog - Step-by-Step Execution

Concept Flow - Adder design (half adder, full adder)

Input bits A, B

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Half Adder: sum = A XOR B

↓

Half Adder: carry = A AND B

↓

For Full Adder: Input carry_in

↓

Full Adder: sum = A XOR B XOR carry_in

↓

Full Adder: carry_out = (A AND B) OR (carry_in AND (A XOR B))

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Output sum and carry_out

The adder takes input bits and calculates sum and carry using logic gates; half adder uses two inputs, full adder adds carry-in for chaining.

Execution Sample

Verilog

module half_adder(input A, input B, output sum, output carry);
  assign sum = A ^ B;
  assign carry = A & B;
endmodule

This half adder module calculates sum and carry for two input bits A and B.

Execution Table

Step	Input A	Input B	Sum (A XOR B)	Carry (A AND B)
1	0	0	0	0
2	0	1	1	0
3	1	0	1	0
4	1	1	0	1
Exit	-	-	-	All input combinations tested

💡 All possible input pairs (A,B) tested for half adder outputs.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4
A	-	0	0	1	1
B	-	0	1	0	1
sum	-	0	1	1	0
carry	-	0	0	0	1

Key Moments - 3 Insights

Why is the sum 0 when both inputs are 1 in the half adder?

Because sum is calculated as XOR of A and B; XOR is 0 when both inputs are the same (see execution_table row 4).

How does the carry output differ from the sum output?

Carry is AND of A and B, so it is 1 only when both inputs are 1 (execution_table row 4), unlike sum which is XOR.

What extra input does a full adder have compared to a half adder?

Full adder has an additional carry_in input to add with A and B, enabling chaining of adders (concept_flow shows this).

Visual Quiz - 3 Questions

Look at the execution_table, what is the sum output when A=1 and B=0?

A 1

B 0

C Undefined

D 2

💡 Hint

Check execution_table row 3 under 'Sum (A XOR B)' column.

At which step does the carry output become 1 in the half adder?

A Step 2

B Step 3

C Step 4

D Never

💡 Hint

Look at the 'Carry (A AND B)' column in execution_table rows.

If carry_in is added to the half adder inputs, what new output is needed?

A A new sum output only

B A carry_out output to handle carry_in

C No new output needed

D An input reset signal

💡 Hint

Refer to concept_flow where full adder adds carry_in and produces carry_out.

Concept Snapshot

Half Adder:
- Inputs: A, B
- sum = A XOR B
- carry = A AND B

Full Adder:
- Inputs: A, B, carry_in
- sum = A XOR B XOR carry_in
- carry_out = (A AND B) OR (carry_in AND (A XOR B))

Used to add bits with carry chaining.

Full Transcript

This visual execution shows how half and full adders work in Verilog. The half adder takes two inputs A and B and calculates sum as XOR and carry as AND. The execution table lists all input combinations and their outputs. The variable tracker shows how inputs and outputs change step by step. Key moments clarify why sum is zero when inputs are both one and how carry differs. The full adder adds a carry_in input and calculates sum and carry_out accordingly. The quiz tests understanding of sum and carry outputs and the role of carry_in. The snapshot summarizes the formulas and inputs for half and full adders.

Practice

1. What does a half adder circuit do in digital logic?

easy

A. Multiplies two bits and outputs the product

B. Adds three bits including carry-in and produces sum and carry

C. Adds two single bits and produces a sum and carry output

D. Stores a single bit of data

Solution

1. Step 1: Understand half adder inputs and outputs

   A half adder takes two bits as input and produces two outputs: sum and carry.

2. Step 2: Compare with other options

   Full adder adds three bits, multiplication and storage are unrelated to half adder.

3. Final Answer:

   Adds two single bits and produces a sum and carry output -> Option C

4. Quick Check:

   Half adder = two bits sum and carry [OK]

Hint: Half adder adds exactly two bits only [OK]

Common Mistakes:

• Confusing half adder with full adder
• Thinking it multiplies bits
• Assuming it stores data

2. Which of the following is the correct Verilog module header for a half adder?

easy

A. module half_adder(output a, output b, input sum, input carry);

B. module half_adder(input a, input b, output sum, output carry);

C. module half_adder(input sum, input carry, output a, output b);

D. module half_adder(input a, output b, input sum, output carry);

Solution

1. Step 1: Identify correct input and output declaration order

   Inputs come first, then outputs. Inputs are 'a' and 'b', outputs are 'sum' and 'carry'.

2. Step 2: Check each option for correct syntax

   module half_adder(input a, input b, output sum, output carry); correctly declares inputs and outputs. Others mix input/output or order incorrectly.

3. Final Answer:

   module half_adder(input a, input b, output sum, output carry); -> Option B

4. Quick Check:

   Inputs first, outputs next in module header [OK]

Hint: Inputs before outputs in module header [OK]

Common Mistakes:

• Swapping input and output keywords
• Wrong order of ports
• Using output as input

3. What is the output sum and carry when a full adder receives inputs a=1, b=1, carry_in=0?

medium

A. sum=1, carry=0

B. sum=0, carry=0

C. sum=1, carry=1

D. sum=0, carry=1

Solution

1. Step 1: Calculate sum for inputs a=1, b=1, carry_in=0

   Sum = a XOR b XOR carry_in = 1 XOR 1 XOR 0 = 0.

2. Step 2: Calculate carry output

   Carry = (a AND b) OR (b AND carry_in) OR (a AND carry_in) = (1 AND 1) OR (1 AND 0) OR (1 AND 0) = 1.

3. Final Answer:

   sum=0, carry=1 -> Option D

4. Quick Check:

   Full adder sum and carry for 1,1,0 = 0,1 [OK]

Hint: Sum is XOR of all inputs, carry is majority logic [OK]

Common Mistakes:

• Forgetting carry_in in sum calculation
• Mixing AND and OR for carry
• Assuming sum equals carry

4. Identify the error in this Verilog full adder snippet:

assign sum = a ^ b ^ carry_in;
assign carry = a & b & carry_in;

medium

A. Carry logic should use OR of AND terms, not AND of all inputs

B. Sum should use AND instead of XOR

C. Carry should be assigned to sum

D. No error, code is correct

Solution

1. Step 1: Review carry logic in full adder

   Carry = (a & b) | (b & carry_in) | (a & carry_in), not a & b & carry_in.

2. Step 2: Compare given code with correct logic

   Given code uses AND of all inputs, which misses cases where two inputs are 1 but third is 0.

3. Final Answer:

   Carry logic should use OR of AND terms, not AND of all inputs -> Option A

4. Quick Check:

   Full adder carry = OR of AND pairs [OK]

Hint: Carry = OR of AND pairs, not AND of all three [OK]

Common Mistakes:

• Using AND for carry instead of OR
• Confusing sum and carry assignments
• Ignoring carry_in in carry logic

5. How can a full adder be constructed using two half adders and one OR gate in Verilog?

hard

A. First half adder adds a and b, second adds sum and carry_in; OR gate combines carries

B. Two half adders add a and carry_in, OR gate combines sums

C. Half adders add carry_in and b, OR gate combines sums and carries

D. Full adder cannot be built from half adders and OR gate

Solution

1. Step 1: Understand half adder roles in full adder

   First half adder adds inputs a and b producing sum1 and carry1.

2. Step 2: Use second half adder and OR gate

   Second half adder adds sum1 and carry_in producing final sum and carry2; OR gate combines carry1 and carry2 for final carry.

3. Final Answer:

   First half adder adds a and b, second adds sum and carry_in; OR gate combines carries -> Option A

4. Quick Check:

   Full adder = 2 half adders + OR gate [OK]

Hint: Chain two half adders, OR their carries for full adder [OK]

Common Mistakes:

• Mixing inputs for half adders
• OR gate combining sums instead of carries
• Believing full adder can't be built from half adders