Adder design (half adder, full adder) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of Half Adder Module

What is the output of the following half adder module when inputs A=1 and B=0?

Verilog

module half_adder(input A, input B, output Sum, output Carry);
  assign Sum = A ^ B;
  assign Carry = A & B;
endmodule

// Inputs: A=1, B=0
// What are Sum and Carry?

A Sum=1, Carry=1

B Sum=1, Carry=0

C Sum=0, Carry=1

D Sum=0, Carry=0

💡 Hint

Recall that Sum is XOR of inputs and Carry is AND of inputs.

The half adder sums two bits. Sum is A XOR B, Carry is A AND B. For A=1 and B=0, XOR is 1 and AND is 0.

❓ Predict Output

intermediate

Full Adder Output for Inputs

Given the full adder module below, what is the output Sum and Carry when A=1, B=1, Cin=1?

Verilog

module full_adder(input A, input B, input Cin, output Sum, output Cout);
  assign Sum = A ^ B ^ Cin;
  assign Cout = (A & B) | (B & Cin) | (A & Cin);
endmodule

// Inputs: A=1, B=1, Cin=1
// What are Sum and Cout?

A Sum=0, Cout=1

B Sum=1, Cout=0

C Sum=1, Cout=1

D Sum=0, Cout=0

💡 Hint

Sum is XOR of all three inputs; Carry out is majority function.

Sum = 1 ^ 1 ^ 1 = 1 ^ 1 = 0 ^ 1 = 1. Carry out is 1 because at least two inputs are 1.

🔧 Debug

advanced

Identify the Error in Full Adder Code

What error will this full adder Verilog code produce when compiled?

Verilog

module full_adder(input A, input B, input Cin, output Sum, output Cout);
  assign Sum = A ^ B ^ Cin;
  assign Cout = (A & B) | (B & Cin) | (A & Cin);
endmodule

A SyntaxError: missing semicolon after Sum assignment

B TypeError: invalid operator ^ for inputs

C No error, code compiles fine

D Runtime error: Cout not assigned

💡 Hint

Check each line for proper syntax punctuation.

The line assigning Sum is missing a semicolon at the end, causing a syntax error.

🧠 Conceptual

advanced

Carry Output Logic in Full Adder

Which expression correctly represents the carry output (Cout) of a full adder?

A Cout = A | B | Cin

B Cout = A & B & Cin

C Cout = A ^ B ^ Cin

D Cout = (A & B) | (B & Cin) | (A & Cin)

💡 Hint

Carry out is true if at least two inputs are 1.

Cout is the majority function of inputs: it is 1 if any two or more inputs are 1, which is expressed by (A & B) | (B & Cin) | (A & Cin).

🚀 Application

expert

Number of Bits in Ripple Carry Adder Output

You design a 4-bit ripple carry adder by connecting four full adders. If inputs A and B are 4-bit numbers and Cin is 0, how many bits does the output sum have?

A 5 bits

B 6 bits

C 3 bits

D 4 bits

💡 Hint

Consider the carry out from the last full adder.

The sum output is 4 bits, but the carry out from the last full adder adds an extra bit, making the total output 5 bits.

Practice

1. What does a half adder circuit do in digital logic?

easy

A. Multiplies two bits and outputs the product

B. Adds three bits including carry-in and produces sum and carry

C. Adds two single bits and produces a sum and carry output

D. Stores a single bit of data

Solution

1. Step 1: Understand half adder inputs and outputs

   A half adder takes two bits as input and produces two outputs: sum and carry.

2. Step 2: Compare with other options

   Full adder adds three bits, multiplication and storage are unrelated to half adder.

3. Final Answer:

   Adds two single bits and produces a sum and carry output -> Option C

4. Quick Check:

   Half adder = two bits sum and carry [OK]

Hint: Half adder adds exactly two bits only [OK]

Common Mistakes:

• Confusing half adder with full adder
• Thinking it multiplies bits
• Assuming it stores data

2. Which of the following is the correct Verilog module header for a half adder?

easy

A. module half_adder(output a, output b, input sum, input carry);

B. module half_adder(input a, input b, output sum, output carry);

C. module half_adder(input sum, input carry, output a, output b);

D. module half_adder(input a, output b, input sum, output carry);

Solution

1. Step 1: Identify correct input and output declaration order

   Inputs come first, then outputs. Inputs are 'a' and 'b', outputs are 'sum' and 'carry'.

2. Step 2: Check each option for correct syntax

   module half_adder(input a, input b, output sum, output carry); correctly declares inputs and outputs. Others mix input/output or order incorrectly.

3. Final Answer:

   module half_adder(input a, input b, output sum, output carry); -> Option B

4. Quick Check:

   Inputs first, outputs next in module header [OK]

Hint: Inputs before outputs in module header [OK]

Common Mistakes:

• Swapping input and output keywords
• Wrong order of ports
• Using output as input

3. What is the output sum and carry when a full adder receives inputs a=1, b=1, carry_in=0?

medium

A. sum=1, carry=0

B. sum=0, carry=0

C. sum=1, carry=1

D. sum=0, carry=1

Solution

1. Step 1: Calculate sum for inputs a=1, b=1, carry_in=0

   Sum = a XOR b XOR carry_in = 1 XOR 1 XOR 0 = 0.

2. Step 2: Calculate carry output

   Carry = (a AND b) OR (b AND carry_in) OR (a AND carry_in) = (1 AND 1) OR (1 AND 0) OR (1 AND 0) = 1.

3. Final Answer:

   sum=0, carry=1 -> Option D

4. Quick Check:

   Full adder sum and carry for 1,1,0 = 0,1 [OK]

Hint: Sum is XOR of all inputs, carry is majority logic [OK]

Common Mistakes:

• Forgetting carry_in in sum calculation
• Mixing AND and OR for carry
• Assuming sum equals carry

4. Identify the error in this Verilog full adder snippet:

assign sum = a ^ b ^ carry_in;
assign carry = a & b & carry_in;

medium

A. Carry logic should use OR of AND terms, not AND of all inputs

B. Sum should use AND instead of XOR

C. Carry should be assigned to sum

D. No error, code is correct

Solution

1. Step 1: Review carry logic in full adder

   Carry = (a & b) | (b & carry_in) | (a & carry_in), not a & b & carry_in.

2. Step 2: Compare given code with correct logic

   Given code uses AND of all inputs, which misses cases where two inputs are 1 but third is 0.

3. Final Answer:

   Carry logic should use OR of AND terms, not AND of all inputs -> Option A

4. Quick Check:

   Full adder carry = OR of AND pairs [OK]

Hint: Carry = OR of AND pairs, not AND of all three [OK]

Common Mistakes:

• Using AND for carry instead of OR
• Confusing sum and carry assignments
• Ignoring carry_in in carry logic

5. How can a full adder be constructed using two half adders and one OR gate in Verilog?

hard

A. First half adder adds a and b, second adds sum and carry_in; OR gate combines carries

B. Two half adders add a and carry_in, OR gate combines sums

C. Half adders add carry_in and b, OR gate combines sums and carries

D. Full adder cannot be built from half adders and OR gate

Solution

1. Step 1: Understand half adder roles in full adder

   First half adder adds inputs a and b producing sum1 and carry1.

2. Step 2: Use second half adder and OR gate

   Second half adder adds sum1 and carry_in producing final sum and carry2; OR gate combines carry1 and carry2 for final carry.

3. Final Answer:

   First half adder adds a and b, second adds sum and carry_in; OR gate combines carries -> Option A

4. Quick Check:

   Full adder = 2 half adders + OR gate [OK]

Hint: Chain two half adders, OR their carries for full adder [OK]

Common Mistakes:

• Mixing inputs for half adders
• OR gate combining sums instead of carries
• Believing full adder can't be built from half adders