Adder design (half adder, full adder) in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a half adder in digital logic?

A half adder is a simple digital circuit that adds two single binary digits and outputs a sum and a carry bit.

beginner

What are the outputs of a half adder?

The outputs are Sum (S) and Carry (C). Sum is the XOR of inputs, and Carry is the AND of inputs.

intermediate

How does a full adder differ from a half adder?

A full adder adds three bits: two input bits and a carry-in bit. It outputs a sum and a carry-out bit.

intermediate

Write the Verilog expression for the sum output of a full adder.

sum = a ^ b ^ cin; // XOR of input bits a, b and carry-in cin

intermediate

What is the carry-out expression in a full adder?

carry_out = (a & b) | (b & cin) | (a & cin); // Carry generated if any two inputs are 1

Which logic gate is used to generate the sum output in a half adder?

A XOR gate

B AND gate

C OR gate

D NOT gate

The sum output of a half adder is generated using an XOR gate.

How many inputs does a full adder take?

A 2

B 4

C 1

D 3

A full adder takes three inputs: two bits to add and a carry-in bit.

What is the carry output of a half adder?

A a AND b

B a OR b

C a XOR b

D NOT a

The carry output of a half adder is the AND of the two input bits.

Which expression correctly represents the carry-out of a full adder?

A a | b | cin

B a ^ b ^ cin

C (a & b) | (b & cin) | (a & cin)

D a & b & cin

The carry-out is generated when any two or more inputs are 1, expressed as (a & b) | (b & cin) | (a & cin).

In Verilog, which operator is used for bitwise XOR?

A |

B ^

C &

D ~

The '^' operator in Verilog is used for bitwise XOR.

Explain the difference between a half adder and a full adder.

Think about how many inputs each adder handles and what outputs they produce.

Describe how you would implement a full adder in Verilog using basic gates.

Recall the expressions for sum and carry-out in a full adder.

Practice

1. What does a half adder circuit do in digital logic?

easy

A. Multiplies two bits and outputs the product

B. Adds three bits including carry-in and produces sum and carry

C. Adds two single bits and produces a sum and carry output

D. Stores a single bit of data

Solution

1. Step 1: Understand half adder inputs and outputs

   A half adder takes two bits as input and produces two outputs: sum and carry.

2. Step 2: Compare with other options

   Full adder adds three bits, multiplication and storage are unrelated to half adder.

3. Final Answer:

   Adds two single bits and produces a sum and carry output -> Option C

4. Quick Check:

   Half adder = two bits sum and carry [OK]

Hint: Half adder adds exactly two bits only [OK]

Common Mistakes:

• Confusing half adder with full adder
• Thinking it multiplies bits
• Assuming it stores data

2. Which of the following is the correct Verilog module header for a half adder?

easy

A. module half_adder(output a, output b, input sum, input carry);

B. module half_adder(input a, input b, output sum, output carry);

C. module half_adder(input sum, input carry, output a, output b);

D. module half_adder(input a, output b, input sum, output carry);

Solution

1. Step 1: Identify correct input and output declaration order

   Inputs come first, then outputs. Inputs are 'a' and 'b', outputs are 'sum' and 'carry'.

2. Step 2: Check each option for correct syntax

   module half_adder(input a, input b, output sum, output carry); correctly declares inputs and outputs. Others mix input/output or order incorrectly.

3. Final Answer:

   module half_adder(input a, input b, output sum, output carry); -> Option B

4. Quick Check:

   Inputs first, outputs next in module header [OK]

Hint: Inputs before outputs in module header [OK]

Common Mistakes:

• Swapping input and output keywords
• Wrong order of ports
• Using output as input

3. What is the output sum and carry when a full adder receives inputs a=1, b=1, carry_in=0?

medium

A. sum=1, carry=0

B. sum=0, carry=0

C. sum=1, carry=1

D. sum=0, carry=1

Solution

1. Step 1: Calculate sum for inputs a=1, b=1, carry_in=0

   Sum = a XOR b XOR carry_in = 1 XOR 1 XOR 0 = 0.

2. Step 2: Calculate carry output

   Carry = (a AND b) OR (b AND carry_in) OR (a AND carry_in) = (1 AND 1) OR (1 AND 0) OR (1 AND 0) = 1.

3. Final Answer:

   sum=0, carry=1 -> Option D

4. Quick Check:

   Full adder sum and carry for 1,1,0 = 0,1 [OK]

Hint: Sum is XOR of all inputs, carry is majority logic [OK]

Common Mistakes:

• Forgetting carry_in in sum calculation
• Mixing AND and OR for carry
• Assuming sum equals carry

4. Identify the error in this Verilog full adder snippet:

assign sum = a ^ b ^ carry_in;
assign carry = a & b & carry_in;

medium

A. Carry logic should use OR of AND terms, not AND of all inputs

B. Sum should use AND instead of XOR

C. Carry should be assigned to sum

D. No error, code is correct

Solution

1. Step 1: Review carry logic in full adder

   Carry = (a & b) | (b & carry_in) | (a & carry_in), not a & b & carry_in.

2. Step 2: Compare given code with correct logic

   Given code uses AND of all inputs, which misses cases where two inputs are 1 but third is 0.

3. Final Answer:

   Carry logic should use OR of AND terms, not AND of all inputs -> Option A

4. Quick Check:

   Full adder carry = OR of AND pairs [OK]

Hint: Carry = OR of AND pairs, not AND of all three [OK]

Common Mistakes:

• Using AND for carry instead of OR
• Confusing sum and carry assignments
• Ignoring carry_in in carry logic

5. How can a full adder be constructed using two half adders and one OR gate in Verilog?

hard

A. First half adder adds a and b, second adds sum and carry_in; OR gate combines carries

B. Two half adders add a and carry_in, OR gate combines sums

C. Half adders add carry_in and b, OR gate combines sums and carries

D. Full adder cannot be built from half adders and OR gate

Solution

1. Step 1: Understand half adder roles in full adder

   First half adder adds inputs a and b producing sum1 and carry1.

2. Step 2: Use second half adder and OR gate

   Second half adder adds sum1 and carry_in producing final sum and carry2; OR gate combines carry1 and carry2 for final carry.

3. Final Answer:

   First half adder adds a and b, second adds sum and carry_in; OR gate combines carries -> Option A

4. Quick Check:

   Full adder = 2 half adders + OR gate [OK]

Hint: Chain two half adders, OR their carries for full adder [OK]

Common Mistakes:

• Mixing inputs for half adders
• OR gate combining sums instead of carries
• Believing full adder can't be built from half adders