Adder design (half adder, full adder) in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a module named half_adder.

Verilog

module [1](input a, input b, output sum, output carry);

Drag options to blanks, or click blank then click option'

Aadder

Bhalf_adder

Cfull_adder

Dsum_carry

Attempts:

3 left

💡 Hint

Common Mistakes

Using full_adder instead of half_adder

Using generic names like adder or sum_carry

The module name for a half adder is half_adder.

2fill in blank

medium

Complete the code to assign the sum output as XOR of inputs a and b.

Verilog

assign sum = a [1] b;

Drag options to blanks, or click blank then click option'

A^

B&

C|

D~

Attempts:

3 left

💡 Hint

Common Mistakes

Using AND (&) instead of XOR

Using OR (|) instead of XOR

The sum in a half adder is the XOR (^) of inputs a and b.

3fill in blank

hard

Fix the error in the carry assignment for the half adder.

Verilog

assign carry = a [1] b;

Drag options to blanks, or click blank then click option'

A&

B^

C|

D~

Attempts:

3 left

💡 Hint

Common Mistakes

Using OR (|) instead of AND

Using XOR (^) instead of AND

The carry output in a half adder is the AND (&) of inputs a and b.

4fill in blank

hard

Fill both blanks to complete the full adder sum and carry assignments.

Verilog

assign sum = a [1] b [2] cin;
assign carry = (a & b) | (b & cin) | (a & cin);

Drag options to blanks, or click blank then click option'

A^

B&

C+

D|

Attempts:

3 left

💡 Hint

Common Mistakes

Using AND or OR operators for sum

Using plus (+) operator which is not bitwise XOR

The sum in a full adder is the XOR of inputs a, b, and cin.

5fill in blank

hard

Fill all three blanks to complete the full adder module port list and internal wire declaration.

Verilog

module full_adder(input [1], input [2], input [3], output sum, output carry);
wire w1, w2, w3;

Drag options to blanks, or click blank then click option'

Aa

Bb

Ccin

Dcout

Attempts:

3 left

💡 Hint

Common Mistakes

Using output names as inputs

Using carry out (cout) as input

The full adder inputs are a, b, and cin (carry in).

Practice

1. What does a half adder circuit do in digital logic?

easy

A. Multiplies two bits and outputs the product

B. Adds three bits including carry-in and produces sum and carry

C. Adds two single bits and produces a sum and carry output

D. Stores a single bit of data

Solution

1. Step 1: Understand half adder inputs and outputs

   A half adder takes two bits as input and produces two outputs: sum and carry.

2. Step 2: Compare with other options

   Full adder adds three bits, multiplication and storage are unrelated to half adder.

3. Final Answer:

   Adds two single bits and produces a sum and carry output -> Option C

4. Quick Check:

   Half adder = two bits sum and carry [OK]

Hint: Half adder adds exactly two bits only [OK]

Common Mistakes:

• Confusing half adder with full adder
• Thinking it multiplies bits
• Assuming it stores data

2. Which of the following is the correct Verilog module header for a half adder?

easy

A. module half_adder(output a, output b, input sum, input carry);

B. module half_adder(input a, input b, output sum, output carry);

C. module half_adder(input sum, input carry, output a, output b);

D. module half_adder(input a, output b, input sum, output carry);

Solution

1. Step 1: Identify correct input and output declaration order

   Inputs come first, then outputs. Inputs are 'a' and 'b', outputs are 'sum' and 'carry'.

2. Step 2: Check each option for correct syntax

   module half_adder(input a, input b, output sum, output carry); correctly declares inputs and outputs. Others mix input/output or order incorrectly.

3. Final Answer:

   module half_adder(input a, input b, output sum, output carry); -> Option B

4. Quick Check:

   Inputs first, outputs next in module header [OK]

Hint: Inputs before outputs in module header [OK]

Common Mistakes:

• Swapping input and output keywords
• Wrong order of ports
• Using output as input

3. What is the output sum and carry when a full adder receives inputs a=1, b=1, carry_in=0?

medium

A. sum=1, carry=0

B. sum=0, carry=0

C. sum=1, carry=1

D. sum=0, carry=1

Solution

1. Step 1: Calculate sum for inputs a=1, b=1, carry_in=0

   Sum = a XOR b XOR carry_in = 1 XOR 1 XOR 0 = 0.

2. Step 2: Calculate carry output

   Carry = (a AND b) OR (b AND carry_in) OR (a AND carry_in) = (1 AND 1) OR (1 AND 0) OR (1 AND 0) = 1.

3. Final Answer:

   sum=0, carry=1 -> Option D

4. Quick Check:

   Full adder sum and carry for 1,1,0 = 0,1 [OK]

Hint: Sum is XOR of all inputs, carry is majority logic [OK]

Common Mistakes:

• Forgetting carry_in in sum calculation
• Mixing AND and OR for carry
• Assuming sum equals carry

4. Identify the error in this Verilog full adder snippet:

assign sum = a ^ b ^ carry_in;
assign carry = a & b & carry_in;

medium

A. Carry logic should use OR of AND terms, not AND of all inputs

B. Sum should use AND instead of XOR

C. Carry should be assigned to sum

D. No error, code is correct

Solution

1. Step 1: Review carry logic in full adder

   Carry = (a & b) | (b & carry_in) | (a & carry_in), not a & b & carry_in.

2. Step 2: Compare given code with correct logic

   Given code uses AND of all inputs, which misses cases where two inputs are 1 but third is 0.

3. Final Answer:

   Carry logic should use OR of AND terms, not AND of all inputs -> Option A

4. Quick Check:

   Full adder carry = OR of AND pairs [OK]

Hint: Carry = OR of AND pairs, not AND of all three [OK]

Common Mistakes:

• Using AND for carry instead of OR
• Confusing sum and carry assignments
• Ignoring carry_in in carry logic

5. How can a full adder be constructed using two half adders and one OR gate in Verilog?

hard

A. First half adder adds a and b, second adds sum and carry_in; OR gate combines carries

B. Two half adders add a and carry_in, OR gate combines sums

C. Half adders add carry_in and b, OR gate combines sums and carries

D. Full adder cannot be built from half adders and OR gate

Solution

1. Step 1: Understand half adder roles in full adder

   First half adder adds inputs a and b producing sum1 and carry1.

2. Step 2: Use second half adder and OR gate

   Second half adder adds sum1 and carry_in producing final sum and carry2; OR gate combines carry1 and carry2 for final carry.

3. Final Answer:

   First half adder adds a and b, second adds sum and carry_in; OR gate combines carries -> Option A

4. Quick Check:

   Full adder = 2 half adders + OR gate [OK]

Hint: Chain two half adders, OR their carries for full adder [OK]

Common Mistakes:

• Mixing inputs for half adders
• OR gate combining sums instead of carries
• Believing full adder can't be built from half adders