Adder design (half adder, full adder) in Verilog - Mini Project: Build & Apply

Adder design (half adder, full adder)

📖 Scenario: You are designing simple digital circuits that add binary numbers. These circuits are called adders. First, you will create a half adder that adds two bits. Then, you will build a full adder that adds three bits including a carry bit.

🎯 Goal: Build a half adder module and then a full adder module in Verilog. The half adder adds two bits and outputs a sum and carry. The full adder adds two bits plus a carry-in and outputs a sum and carry-out.

📋 What You'll Learn

Create a half adder module named half_adder with inputs a and b and outputs sum and carry.

Create a full adder module named full_adder with inputs a, b, and cin and outputs sum and cout.

Use the half adder module inside the full adder module to build the logic.

Print the outputs of the full adder for all input combinations.

💡 Why This Matters

🌍 Real World

Adders are fundamental building blocks in digital electronics used in calculators, computers, and digital signal processors to perform arithmetic operations.

💼 Career

Understanding how to design and test adders is essential for hardware engineers and FPGA/ASIC designers working on arithmetic logic units and digital circuit design.

1

Create the half adder module

Write a Verilog module named half_adder with inputs a and b and outputs sum and carry. Use assign statements to set sum as the XOR of a and b, and carry as the AND of a and b.

Verilog

// Your code here
// Create module half_adder with inputs a, b and outputs sum, carry
// sum = a XOR b
// carry = a AND b

Hint

Remember, XOR (^) gives sum without carry, AND (&) gives carry.

2

Create the full adder module using two half adders

Write a Verilog module named full_adder with inputs a, b, and cin and outputs sum and cout. Instantiate two half_adder modules inside it. Connect the first half adder to inputs a and b. Connect the second half adder to the first half adder's sum and cin. Use an or gate to combine the carry outputs of both half adders into cout.

Verilog

// Your code here
// Create module full_adder with inputs a, b, cin and outputs sum, cout
// Use two half_adder instances
// Use or gate for cout

Hint

Use wires to connect outputs of half adders. The final carry is OR of both half adder carries.

3

Create a testbench to check all input combinations

Write a Verilog testbench module named test_full_adder. Declare reg variables a, b, and cin. Declare wire variables sum and cout. Instantiate the full_adder module. Use a for loop or multiple statements to assign all combinations of a, b, and cin from 0 to 1. Use $display to print the inputs and outputs for each combination.

Verilog

// Your code here
// Create testbench module test_full_adder
// Declare reg a, b, cin
// Declare wire sum, cout
// Instantiate full_adder
// Use initial block to assign all input combinations
// Use $display to print inputs and outputs

Hint

Use a loop from 0 to 7 to cover all 3-bit input combinations. Use delays (#1) to allow signals to update before printing.

4

Run the testbench and display the results

Run the test_full_adder module to print the sum and carry outputs for all input combinations. Use the $display statements already in the testbench to show the results.

Verilog

// Your code here
// Run the testbench module test_full_adder
// Observe the printed output

Hint

The output shows all possible sums and carries for inputs a, b, and cin.

Practice

1. What does a half adder circuit do in digital logic?

easy

A. Multiplies two bits and outputs the product

B. Adds three bits including carry-in and produces sum and carry

C. Adds two single bits and produces a sum and carry output

D. Stores a single bit of data

Solution

1. Step 1: Understand half adder inputs and outputs

   A half adder takes two bits as input and produces two outputs: sum and carry.

2. Step 2: Compare with other options

   Full adder adds three bits, multiplication and storage are unrelated to half adder.

3. Final Answer:

   Adds two single bits and produces a sum and carry output -> Option C

4. Quick Check:

   Half adder = two bits sum and carry [OK]

Hint: Half adder adds exactly two bits only [OK]

Common Mistakes:

• Confusing half adder with full adder
• Thinking it multiplies bits
• Assuming it stores data

2. Which of the following is the correct Verilog module header for a half adder?

easy

A. module half_adder(output a, output b, input sum, input carry);

B. module half_adder(input a, input b, output sum, output carry);

C. module half_adder(input sum, input carry, output a, output b);

D. module half_adder(input a, output b, input sum, output carry);

Solution

1. Step 1: Identify correct input and output declaration order

   Inputs come first, then outputs. Inputs are 'a' and 'b', outputs are 'sum' and 'carry'.

2. Step 2: Check each option for correct syntax

   module half_adder(input a, input b, output sum, output carry); correctly declares inputs and outputs. Others mix input/output or order incorrectly.

3. Final Answer:

   module half_adder(input a, input b, output sum, output carry); -> Option B

4. Quick Check:

   Inputs first, outputs next in module header [OK]

Hint: Inputs before outputs in module header [OK]

Common Mistakes:

• Swapping input and output keywords
• Wrong order of ports
• Using output as input

3. What is the output sum and carry when a full adder receives inputs a=1, b=1, carry_in=0?

medium

A. sum=1, carry=0

B. sum=0, carry=0

C. sum=1, carry=1

D. sum=0, carry=1

Solution

1. Step 1: Calculate sum for inputs a=1, b=1, carry_in=0

   Sum = a XOR b XOR carry_in = 1 XOR 1 XOR 0 = 0.

2. Step 2: Calculate carry output

   Carry = (a AND b) OR (b AND carry_in) OR (a AND carry_in) = (1 AND 1) OR (1 AND 0) OR (1 AND 0) = 1.

3. Final Answer:

   sum=0, carry=1 -> Option D

4. Quick Check:

   Full adder sum and carry for 1,1,0 = 0,1 [OK]

Hint: Sum is XOR of all inputs, carry is majority logic [OK]

Common Mistakes:

• Forgetting carry_in in sum calculation
• Mixing AND and OR for carry
• Assuming sum equals carry

4. Identify the error in this Verilog full adder snippet:

assign sum = a ^ b ^ carry_in;
assign carry = a & b & carry_in;

medium

A. Carry logic should use OR of AND terms, not AND of all inputs

B. Sum should use AND instead of XOR

C. Carry should be assigned to sum

D. No error, code is correct

Solution

1. Step 1: Review carry logic in full adder

   Carry = (a & b) | (b & carry_in) | (a & carry_in), not a & b & carry_in.

2. Step 2: Compare given code with correct logic

   Given code uses AND of all inputs, which misses cases where two inputs are 1 but third is 0.

3. Final Answer:

   Carry logic should use OR of AND terms, not AND of all inputs -> Option A

4. Quick Check:

   Full adder carry = OR of AND pairs [OK]

Hint: Carry = OR of AND pairs, not AND of all three [OK]

Common Mistakes:

• Using AND for carry instead of OR
• Confusing sum and carry assignments
• Ignoring carry_in in carry logic

5. How can a full adder be constructed using two half adders and one OR gate in Verilog?

hard

A. First half adder adds a and b, second adds sum and carry_in; OR gate combines carries

B. Two half adders add a and carry_in, OR gate combines sums

C. Half adders add carry_in and b, OR gate combines sums and carries

D. Full adder cannot be built from half adders and OR gate

Solution

1. Step 1: Understand half adder roles in full adder

   First half adder adds inputs a and b producing sum1 and carry1.

2. Step 2: Use second half adder and OR gate

   Second half adder adds sum1 and carry_in producing final sum and carry2; OR gate combines carry1 and carry2 for final carry.

3. Final Answer:

   First half adder adds a and b, second adds sum and carry_in; OR gate combines carries -> Option A

4. Quick Check:

   Full adder = 2 half adders + OR gate [OK]

Hint: Chain two half adders, OR their carries for full adder [OK]

Common Mistakes:

• Mixing inputs for half adders
• OR gate combining sums instead of carries
• Believing full adder can't be built from half adders