Top module integration pattern in Verilog - Step-by-Step Execution

Concept Flow - Top module integration pattern

Define Submodules

↓

Declare Top Module

↓

Declare Inputs/Outputs

↓

Instantiate Submodules

↓

Connect Signals

↓

End Top Module

The top module integration pattern shows how to define a top-level module that includes submodules, connects their inputs and outputs, and integrates the design.

Execution Sample

Verilog

module adder(input wire a, b, output wire sum);
  assign sum = a ^ b; // Corrected to bitwise XOR for 1-bit addition
endmodule

module top(input wire x, y, output wire z);
  adder u_adder(.a(x), .b(y), .sum(z));
endmodule

This code defines a simple adder submodule and a top module that integrates it by connecting inputs and outputs.

Execution Table

Step	Action	Evaluation	Result
1	Define submodule 'adder'	Create module with inputs a,b and output sum	Submodule 'adder' ready
2	Define top module 'top'	Create module with inputs x,y and output z	Top module 'top' ready
3	Instantiate 'adder' inside 'top'	Connect a->x, b->y, sum->z	Submodule instance u_adder created
4	Connect signals	x,y inputs drive a,b; sum output drives z	Signal connections established
5	End top module	Complete module definition	Top module integration complete

💡 All submodules instantiated and connected; top module ready for synthesis or simulation

Variable Tracker

Signal	Initial	After Instantiation	Final
a	undefined	connected to x	connected to x
b	undefined	connected to y	connected to y
sum	undefined	connected to z	connected to z
x	input	input	input
y	input	input	input
z	output	output	output

Key Moments - 3 Insights

Why do we connect submodule ports to top module signals?

Connecting submodule ports to top module signals allows data to flow between modules. See execution_table step 3 where 'a' connects to 'x' and 'b' to 'y'. Without this, submodules can't communicate.

What happens if we forget to instantiate a submodule in the top module?

If a submodule is not instantiated, its functionality is missing from the design. Execution_table step 3 shows instantiation; skipping it means no hardware is generated for that submodule.

Can the top module have inputs/outputs different from submodules?

Yes, the top module defines the external interface. Submodules are connected internally. Execution_table step 2 shows top inputs x,y and output z, which map to submodule ports in step 3.

Visual Quiz - 3 Questions

Look at the execution_table, at which step is the submodule 'adder' instantiated inside the top module?

A Step 3

B Step 1

C Step 4

D Step 5

💡 Hint

Check the 'Action' column in execution_table for 'Instantiate' keyword.

According to variable_tracker, what is the connection status of signal 'sum' after instantiation?

A Connected to x

B Connected to y

C Connected to z

D Undefined

💡 Hint

Look at the 'sum' row under 'After Instantiation' column in variable_tracker.

If we remove the connection between 'sum' and 'z', what would change in the execution_table?

A Step 1 would not define submodule

B Step 3 would show no connection for sum->z

C Step 2 would fail to define top module

D Step 5 would be skipped

💡 Hint

Focus on the 'Evaluation' column in step 3 about signal connections.

Concept Snapshot

Top module integration pattern in Verilog:
- Define submodules separately
- Declare top module with inputs/outputs
- Instantiate submodules inside top
- Connect submodule ports to top signals
- Complete top module for integration

Full Transcript

This visual execution shows how to integrate submodules into a top module in Verilog. First, submodules like 'adder' are defined with their inputs and outputs. Then, the top module is declared with its own inputs and outputs. Inside the top module, submodules are instantiated and their ports are connected to the top module's signals. The variable tracker shows how signals like 'a', 'b', and 'sum' connect to 'x', 'y', and 'z' respectively. Key moments clarify why connections are necessary and what happens if instantiation is missed. The quiz tests understanding of instantiation steps and signal connections. This pattern is essential for building complex hardware designs by combining smaller modules.

Practice

1. What is the main purpose of the top module integration pattern in Verilog?

easy

A. To combine smaller modules into one organized system

B. To write testbench code for simulation

C. To declare variables inside a module

D. To define timing constraints for synthesis

Solution

1. Step 1: Understand the role of the top module

   The top module acts as a container that connects smaller modules together.

2. Step 2: Recognize the benefit of integration

   Integrating modules in the top module keeps the design organized and easier to manage.

3. Final Answer:

   To combine smaller modules into one organized system -> Option A

4. Quick Check:

   Top module integration = combining modules [OK]

Hint: Top module connects smaller modules into one system [OK]

Common Mistakes:

• Confusing top module with testbench
• Thinking top module declares variables only
• Mixing synthesis constraints with integration

2. Which of the following is the correct way to instantiate a submodule named alu inside a top module in Verilog?

easy

A. inst alu alu_instance();

B. alu_instance alu();

C. module alu_instance();

D. alu alu_instance();

Solution

1. Step 1: Recall Verilog module instantiation syntax

   The correct syntax is: module_name instance_name();

2. Step 2: Match syntax to options

   alu alu_instance(); uses alu alu_instance(); which matches the correct pattern.

3. Final Answer:

   alu alu_instance(); -> Option D

4. Quick Check:

   ModuleName InstanceName(); = correct instantiation [OK]

Hint: Use 'module_name instance_name();' to instantiate [OK]

Common Mistakes:

• Swapping instance and module names
• Using 'module' keyword during instantiation
• Adding extra keywords like 'inst'

3. Given the following top module code, what is the width of the output signal result?

module alu(input [3:0] a, input [3:0] b, output [4:0] sum);
  assign sum = a + b;
endmodule

module top();
  wire [4:0] result;
  wire [3:0] x = 4'b1010;
  wire [3:0] y = 4'b0101;
  alu alu_inst(.a(x), .b(y), .sum(result));
endmodule

medium

A. 4 bits

B. 5 bits

C. 3 bits

D. 8 bits

Solution

1. Step 1: Check the output width in the submodule

   The alu module defines sum as 5 bits wide: output [4:0] sum.

2. Step 2: Confirm connection in top module

   The top module connects result wire as 5 bits wide to sum.

3. Final Answer:

   5 bits -> Option B

4. Quick Check:

   Output width matches submodule definition = 5 bits [OK]

Hint: Output width matches submodule port width [OK]

Common Mistakes:

• Assuming output width equals input width
• Ignoring declared wire width in top module
• Confusing bit ranges like [4:0] as 4 bits

4. Identify the error in this top module integration code:

module adder(input [3:0] a, input [3:0] b, output [4:0] sum);
  assign sum = a + b;
endmodule

module top();
  wire [4:0] result;
  wire [3:0] x = 4'b0011;
  wire [3:0] y = 4'b0101;
  adder add_inst(.a(x), .b(y), .sum(sum));
endmodule

medium

A. Incorrect bit width for 'result'

B. Module 'adder' is missing ports

C. Signal 'sum' is not declared in top module

D. Instance name 'add_inst' is invalid

Solution

1. Step 1: Check port connections in top module

   The instance connects .sum(sum), but sum is not declared in top module.

2. Step 2: Verify declared signals

   Only result is declared as 5-bit wire, but not sum.

3. Final Answer:

   Signal 'sum' is not declared in top module -> Option C

4. Quick Check:

   Port connection must match declared signals [OK]

Hint: Check all connected signals are declared in top module [OK]

Common Mistakes:

• Using undeclared signals in port connections
• Assuming instance names affect correctness
• Ignoring port width mismatches

5. You want to integrate two modules, counter and display, in a top module. The counter outputs a 4-bit count signal, and display takes a 4-bit input to show the count. Which of the following top module code snippets correctly connects these modules?

hard

A. module top();
wire [3:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

B. module top();
wire count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

C. module top();
wire [4:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

D. module top();
reg [3:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

Solution

1. Step 1: Match signal widths

   The counter outputs 4 bits, so count must be 4 bits wide wire.

2. Step 2: Use wire for inter-module connection

   Signals connecting modules should be wires, not regs, unless driven inside the module.

3. Step 3: Verify port names and connections

   module top(); wire [3:0] count; counter c1(.count_out(count)); display d1(.data_in(count)); endmodule correctly connects count_out to count and data_in to count.

4. Final Answer:

   module top(); wire [3:0] count; counter c1(.count_out(count)); display d1(.data_in(count)); endmodule -> Option A

5. Quick Check:

   Correct width and wire type for inter-module signals [OK]

Hint: Use wire with correct width to connect modules [OK]

Common Mistakes:

• Using reg instead of wire for connections
• Mismatching signal widths
• Declaring signals with wrong bit size