Top module integration pattern in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the top module with input clk.

Verilog

module top_module([1]);
  input clk;
endmodule

Drag options to blanks, or click blank then click option'

Arst

Bclk

Cdata_in

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using reset or data signals instead of clock as input.

The top module declares clk as input to connect clock signal.

2fill in blank

medium

Complete the code to instantiate the submodule named alu inside the top module.

Verilog

alu u_alu(.clk([1]));

Drag options to blanks, or click blank then click option'

Aclk

Brst

Cdata

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Connecting reset or other signals instead of clock.

The submodule alu connects its clock port to the top module's clk.

3fill in blank

hard

Fix the error in the port declaration of the top module to include reset input.

Verilog

module top_module(input clk, [1]);
endmodule

Drag options to blanks, or click blank then click option'

Arst

Benable

Crst_n

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using ambiguous or incomplete names like rst or enable.

The standard reset input is named reset to clearly indicate its function.

4fill in blank

hard

Fill both blanks to connect the submodule ports clk and reset to top module signals.

Verilog

submodule u_sub(.clk([1]), .reset([2]));

Drag options to blanks, or click blank then click option'

Aclk

Brst

Creset

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing reset and rst signals or using enable incorrectly.

The submodule's clk port connects to top's clk, and reset port connects to top's reset.

5fill in blank

hard

Fill all three blanks to create a dictionary comprehension that maps signal names to their widths if width > 1.

Verilog

wire [[1]-1:0] data_[2];
assign width_map = '{ [3]: [1] for [3] in signals if [1] > 1 };

Drag options to blanks, or click blank then click option'

Awidth

Bname

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up variable names or using wrong keys in comprehension.

The wire width uses width, the signal name is name, and the dictionary comprehension maps name to width if width is greater than 1.

Practice

1. What is the main purpose of the top module integration pattern in Verilog?

easy

A. To combine smaller modules into one organized system

B. To write testbench code for simulation

C. To declare variables inside a module

D. To define timing constraints for synthesis

Solution

1. Step 1: Understand the role of the top module

   The top module acts as a container that connects smaller modules together.

2. Step 2: Recognize the benefit of integration

   Integrating modules in the top module keeps the design organized and easier to manage.

3. Final Answer:

   To combine smaller modules into one organized system -> Option A

4. Quick Check:

   Top module integration = combining modules [OK]

Hint: Top module connects smaller modules into one system [OK]

Common Mistakes:

• Confusing top module with testbench
• Thinking top module declares variables only
• Mixing synthesis constraints with integration

2. Which of the following is the correct way to instantiate a submodule named alu inside a top module in Verilog?

easy

A. inst alu alu_instance();

B. alu_instance alu();

C. module alu_instance();

D. alu alu_instance();

Solution

1. Step 1: Recall Verilog module instantiation syntax

   The correct syntax is: module_name instance_name();

2. Step 2: Match syntax to options

   alu alu_instance(); uses alu alu_instance(); which matches the correct pattern.

3. Final Answer:

   alu alu_instance(); -> Option D

4. Quick Check:

   ModuleName InstanceName(); = correct instantiation [OK]

Hint: Use 'module_name instance_name();' to instantiate [OK]

Common Mistakes:

• Swapping instance and module names
• Using 'module' keyword during instantiation
• Adding extra keywords like 'inst'

3. Given the following top module code, what is the width of the output signal result?

module alu(input [3:0] a, input [3:0] b, output [4:0] sum);
  assign sum = a + b;
endmodule

module top();
  wire [4:0] result;
  wire [3:0] x = 4'b1010;
  wire [3:0] y = 4'b0101;
  alu alu_inst(.a(x), .b(y), .sum(result));
endmodule

medium

A. 4 bits

B. 5 bits

C. 3 bits

D. 8 bits

Solution

1. Step 1: Check the output width in the submodule

   The alu module defines sum as 5 bits wide: output [4:0] sum.

2. Step 2: Confirm connection in top module

   The top module connects result wire as 5 bits wide to sum.

3. Final Answer:

   5 bits -> Option B

4. Quick Check:

   Output width matches submodule definition = 5 bits [OK]

Hint: Output width matches submodule port width [OK]

Common Mistakes:

• Assuming output width equals input width
• Ignoring declared wire width in top module
• Confusing bit ranges like [4:0] as 4 bits

4. Identify the error in this top module integration code:

module adder(input [3:0] a, input [3:0] b, output [4:0] sum);
  assign sum = a + b;
endmodule

module top();
  wire [4:0] result;
  wire [3:0] x = 4'b0011;
  wire [3:0] y = 4'b0101;
  adder add_inst(.a(x), .b(y), .sum(sum));
endmodule

medium

A. Incorrect bit width for 'result'

B. Module 'adder' is missing ports

C. Signal 'sum' is not declared in top module

D. Instance name 'add_inst' is invalid

Solution

1. Step 1: Check port connections in top module

   The instance connects .sum(sum), but sum is not declared in top module.

2. Step 2: Verify declared signals

   Only result is declared as 5-bit wire, but not sum.

3. Final Answer:

   Signal 'sum' is not declared in top module -> Option C

4. Quick Check:

   Port connection must match declared signals [OK]

Hint: Check all connected signals are declared in top module [OK]

Common Mistakes:

• Using undeclared signals in port connections
• Assuming instance names affect correctness
• Ignoring port width mismatches

5. You want to integrate two modules, counter and display, in a top module. The counter outputs a 4-bit count signal, and display takes a 4-bit input to show the count. Which of the following top module code snippets correctly connects these modules?

hard

A. module top();
wire [3:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

B. module top();
wire count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

C. module top();
wire [4:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

D. module top();
reg [3:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

Solution

1. Step 1: Match signal widths

   The counter outputs 4 bits, so count must be 4 bits wide wire.

2. Step 2: Use wire for inter-module connection

   Signals connecting modules should be wires, not regs, unless driven inside the module.

3. Step 3: Verify port names and connections

   module top(); wire [3:0] count; counter c1(.count_out(count)); display d1(.data_in(count)); endmodule correctly connects count_out to count and data_in to count.

4. Final Answer:

   module top(); wire [3:0] count; counter c1(.count_out(count)); display d1(.data_in(count)); endmodule -> Option A

5. Quick Check:

   Correct width and wire type for inter-module signals [OK]

Hint: Use wire with correct width to connect modules [OK]

Common Mistakes:

• Using reg instead of wire for connections
• Mismatching signal widths
• Declaring signals with wrong bit size