Top module integration pattern in Verilog - Mini Project: Build & Apply

Top Module Integration Pattern in Verilog

📖 Scenario: You are designing a simple digital system that combines two smaller modules: a counter and a comparator. The top module will integrate these two modules to create a system that counts up and signals when the count reaches a preset value.

🎯 Goal: Build a top-level Verilog module that integrates a counter module and a comparator module. The top module should instantiate both modules, connect their inputs and outputs properly, and output a signal when the counter value matches the preset comparator value.

📋 What You'll Learn

Create a counter module with a 4-bit output count and an input clock clk.

Create a comparator module with inputs value and preset, and output match that is high when value == preset.

Create a top module called top_module that instantiates counter and comparator.

Connect the count output of counter to the value input of comparator.

Use a 4-bit input preset in top_module to connect to the preset input of comparator.

Output the match signal from comparator as top_match from top_module.

💡 Why This Matters

🌍 Real World

Top module integration is used in hardware design to combine smaller functional blocks into a complete system, like combining processors, memory, and peripherals.

💼 Career

Understanding how to integrate modules is essential for FPGA and ASIC design engineers who build complex digital circuits.

1

Create the counter module

Write a Verilog module called counter with inputs clk and output count as a 4-bit register. On every positive edge of clk, increment count by 1. Initialize count to 0.

Verilog

// Your code here

Hint

Use always @(posedge clk) to update the count on clock edges.

2

Create the comparator module

Write a Verilog module called comparator with 4-bit inputs value and preset, and output match. The output match should be high when value equals preset, otherwise low.

Verilog

module counter(input wire clk, output reg [3:0] count);
    initial count = 4'b0000;
    always @(posedge clk) begin
        count <= count + 1;
    end
endmodule

// Your code here

Hint

Use a continuous assignment with assign to compare value and preset.

3

Create the top module top_module and instantiate submodules

Write a Verilog module called top_module with inputs clk and 4-bit preset, and output top_match. Instantiate the counter and comparator modules inside. Connect counter's count output to comparator's value input. Connect preset input to comparator's preset input. Connect comparator's match output to top_match output.

Verilog

module counter(input wire clk, output reg [3:0] count);
    initial count = 4'b0000;
    always @(posedge clk) begin
        count <= count + 1;
    end
endmodule

module comparator(input wire [3:0] value, input wire [3:0] preset, output wire match);
    assign match = (value == preset) ? 1'b1 : 1'b0;
endmodule

// Your code here

Hint

Use named port connections to connect signals between modules.

4

Output the top_match signal

Add a testbench module to simulate the top_module. Instantiate top_module with a clock signal and preset value 4'b0101. Run the simulation for enough clock cycles to see top_match go high when the count reaches the preset. Use $display to print the count and top_match values on each clock cycle.

Verilog

module counter(input wire clk, output reg [3:0] count);
    initial count = 4'b0000;
    always @(posedge clk) begin
        count <= count + 1;
    end
endmodule

module comparator(input wire [3:0] value, input wire [3:0] preset, output wire match);
    assign match = (value == preset) ? 1'b1 : 1'b0;
endmodule

module top_module(input wire clk, input wire [3:0] preset, output wire top_match);
    wire [3:0] count;
    counter u_counter(.clk(clk), .count(count));
    comparator u_comparator(.value(count), .preset(preset), .match(top_match));
endmodule

// Your code here

Hint

Use a clock that toggles every 5 time units and print values at each positive edge.

Practice

1. What is the main purpose of the top module integration pattern in Verilog?

easy

A. To combine smaller modules into one organized system

B. To write testbench code for simulation

C. To declare variables inside a module

D. To define timing constraints for synthesis

Solution

1. Step 1: Understand the role of the top module

   The top module acts as a container that connects smaller modules together.

2. Step 2: Recognize the benefit of integration

   Integrating modules in the top module keeps the design organized and easier to manage.

3. Final Answer:

   To combine smaller modules into one organized system -> Option A

4. Quick Check:

   Top module integration = combining modules [OK]

Hint: Top module connects smaller modules into one system [OK]

Common Mistakes:

• Confusing top module with testbench
• Thinking top module declares variables only
• Mixing synthesis constraints with integration

2. Which of the following is the correct way to instantiate a submodule named alu inside a top module in Verilog?

easy

A. inst alu alu_instance();

B. alu_instance alu();

C. module alu_instance();

D. alu alu_instance();

Solution

1. Step 1: Recall Verilog module instantiation syntax

   The correct syntax is: module_name instance_name();

2. Step 2: Match syntax to options

   alu alu_instance(); uses alu alu_instance(); which matches the correct pattern.

3. Final Answer:

   alu alu_instance(); -> Option D

4. Quick Check:

   ModuleName InstanceName(); = correct instantiation [OK]

Hint: Use 'module_name instance_name();' to instantiate [OK]

Common Mistakes:

• Swapping instance and module names
• Using 'module' keyword during instantiation
• Adding extra keywords like 'inst'

3. Given the following top module code, what is the width of the output signal result?

module alu(input [3:0] a, input [3:0] b, output [4:0] sum);
  assign sum = a + b;
endmodule

module top();
  wire [4:0] result;
  wire [3:0] x = 4'b1010;
  wire [3:0] y = 4'b0101;
  alu alu_inst(.a(x), .b(y), .sum(result));
endmodule

medium

A. 4 bits

B. 5 bits

C. 3 bits

D. 8 bits

Solution

1. Step 1: Check the output width in the submodule

   The alu module defines sum as 5 bits wide: output [4:0] sum.

2. Step 2: Confirm connection in top module

   The top module connects result wire as 5 bits wide to sum.

3. Final Answer:

   5 bits -> Option B

4. Quick Check:

   Output width matches submodule definition = 5 bits [OK]

Hint: Output width matches submodule port width [OK]

Common Mistakes:

• Assuming output width equals input width
• Ignoring declared wire width in top module
• Confusing bit ranges like [4:0] as 4 bits

4. Identify the error in this top module integration code:

module adder(input [3:0] a, input [3:0] b, output [4:0] sum);
  assign sum = a + b;
endmodule

module top();
  wire [4:0] result;
  wire [3:0] x = 4'b0011;
  wire [3:0] y = 4'b0101;
  adder add_inst(.a(x), .b(y), .sum(sum));
endmodule

medium

A. Incorrect bit width for 'result'

B. Module 'adder' is missing ports

C. Signal 'sum' is not declared in top module

D. Instance name 'add_inst' is invalid

Solution

1. Step 1: Check port connections in top module

   The instance connects .sum(sum), but sum is not declared in top module.

2. Step 2: Verify declared signals

   Only result is declared as 5-bit wire, but not sum.

3. Final Answer:

   Signal 'sum' is not declared in top module -> Option C

4. Quick Check:

   Port connection must match declared signals [OK]

Hint: Check all connected signals are declared in top module [OK]

Common Mistakes:

• Using undeclared signals in port connections
• Assuming instance names affect correctness
• Ignoring port width mismatches

5. You want to integrate two modules, counter and display, in a top module. The counter outputs a 4-bit count signal, and display takes a 4-bit input to show the count. Which of the following top module code snippets correctly connects these modules?

hard

A. module top();
wire [3:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

B. module top();
wire count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

C. module top();
wire [4:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

D. module top();
reg [3:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

Solution

1. Step 1: Match signal widths

   The counter outputs 4 bits, so count must be 4 bits wide wire.

2. Step 2: Use wire for inter-module connection

   Signals connecting modules should be wires, not regs, unless driven inside the module.

3. Step 3: Verify port names and connections

   module top(); wire [3:0] count; counter c1(.count_out(count)); display d1(.data_in(count)); endmodule correctly connects count_out to count and data_in to count.

4. Final Answer:

   module top(); wire [3:0] count; counter c1(.count_out(count)); display d1(.data_in(count)); endmodule -> Option A

5. Quick Check:

   Correct width and wire type for inter-module signals [OK]

Hint: Use wire with correct width to connect modules [OK]

Common Mistakes:

• Using reg instead of wire for connections
• Mismatching signal widths
• Declaring signals with wrong bit size