Top module integration pattern in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this top module simulation?

Consider this Verilog top module integrating two submodules. What will be the value of out_signal after one clock cycle?

Verilog

module submoduleA(input wire clk, input wire in_signal, output reg out_signal);
  always @(posedge clk) begin
    out_signal <= ~in_signal;
  end
endmodule

module submoduleB(input wire clk, input wire in_signal, output reg out_signal);
  always @(posedge clk) begin
    out_signal <= in_signal;
  end
endmodule

module top_module(input wire clk, input wire in_signal, output wire out_signal);
  wire a_out;
  wire b_out;

  submoduleA uA(.clk(clk), .in_signal(in_signal), .out_signal(a_out));
  submoduleB uB(.clk(clk), .in_signal(a_out), .out_signal(b_out));

  assign out_signal = b_out;
endmodule

// Testbench snippet:
// clk = 0 -> 1 (rising edge), in_signal = 1
// What is out_signal after this clock edge?

A out_signal = 0

B out_signal = unknown (X)

C out_signal = 1

D out_signal = retains previous value

💡 Hint

Trace the signal through submoduleA and then submoduleB on the clock rising edge.

At the rising edge, submoduleA outputs the negation of in_signal, so a_out = ~1 = 0. Then submoduleB outputs a_out, so b_out = 0. Therefore, out_signal = 0.

🧠 Conceptual

intermediate

Which statement best describes the role of the top module in Verilog integration?

In a Verilog design, what is the primary role of the top module when integrating multiple submodules?

A It defines the clock frequency for all submodules internally.

B It replaces the need for testbenches in simulation.

C It synthesizes the design into hardware gates automatically.

D It connects submodules by wiring their inputs and outputs together.

💡 Hint

Think about how modules communicate in hardware design.

The top module acts as a container that connects submodules by wiring their inputs and outputs, enabling them to work together as a system.

🔧 Debug

advanced

Why does this top module cause a synthesis error?

Examine this top module code snippet. Why will synthesis tools report an error?

Verilog

module top_module(input wire clk, input wire rst, output wire out_signal);
  wire internal_signal;

  submoduleA uA(.clk(clk), .in_signal(internal_signal), .out_signal(out_signal));
  submoduleB uB(.clk(clk), .in_signal(out_signal), .out_signal(internal_signal));
endmodule

A The output port is declared as wire instead of reg.

B The module is missing a reset connection to submodules.

C There is a combinational loop between submoduleA and submoduleB signals.

D The clock input is not connected to submoduleB.

💡 Hint

Look for signal dependencies that form a cycle without registers.

The signals internal_signal and out_signal form a combinational loop between submoduleA and submoduleB, which is not allowed in synthesis.

📝 Syntax

advanced

Which option correctly instantiates a submodule with named port connections?

Given a submodule submoduleX with ports input clk, input data_in, and output data_out, which instantiation inside a top module is syntactically correct?

A submoduleX uX(.clk(clk), .data_in(data_in), .data_out(data_out));

B submoduleX uX(.clk => clk, .data_in => data_in, .data_out => data_out);

C submoduleX uX(clk => clk, data_in => data_in, data_out => data_out);

D submoduleX uX(clk, data_in, data_out);

💡 Hint

Recall the correct syntax for named port connections in Verilog.

Named port connections use the dot . followed by the port name and parentheses enclosing the signal name, like .clk(clk).

🚀 Application

expert

How many wires are needed to connect 3 submodules in a top module?

You have three submodules: A, B, and C. A outputs a 4-bit bus to B, B outputs a 2-bit bus to C, and C outputs a 1-bit signal to the top module output. How many wire declarations are needed inside the top module to connect these submodules?

A 7 wires: four 1-bit for A->B, two 1-bit for B->C, one 1-bit for C->top

B 3 wires: one 4-bit, one 2-bit, one 1-bit

C 6 wires: three 1-bit for A->B, two 1-bit for B->C, one 1-bit for C->top

D 1 wire: a 7-bit bus combining all signals

💡 Hint

Consider that buses count as single wires with multiple bits.

Each bus is declared as one wire with the appropriate bit width. So one 4-bit wire connects A to B, one 2-bit wire connects B to C, and one 1-bit wire connects C to the top output, totaling 3 wires.

Practice

1. What is the main purpose of the top module integration pattern in Verilog?

easy

A. To combine smaller modules into one organized system

B. To write testbench code for simulation

C. To declare variables inside a module

D. To define timing constraints for synthesis

Solution

1. Step 1: Understand the role of the top module

   The top module acts as a container that connects smaller modules together.

2. Step 2: Recognize the benefit of integration

   Integrating modules in the top module keeps the design organized and easier to manage.

3. Final Answer:

   To combine smaller modules into one organized system -> Option A

4. Quick Check:

   Top module integration = combining modules [OK]

Hint: Top module connects smaller modules into one system [OK]

Common Mistakes:

• Confusing top module with testbench
• Thinking top module declares variables only
• Mixing synthesis constraints with integration

2. Which of the following is the correct way to instantiate a submodule named alu inside a top module in Verilog?

easy

A. inst alu alu_instance();

B. alu_instance alu();

C. module alu_instance();

D. alu alu_instance();

Solution

1. Step 1: Recall Verilog module instantiation syntax

   The correct syntax is: module_name instance_name();

2. Step 2: Match syntax to options

   alu alu_instance(); uses alu alu_instance(); which matches the correct pattern.

3. Final Answer:

   alu alu_instance(); -> Option D

4. Quick Check:

   ModuleName InstanceName(); = correct instantiation [OK]

Hint: Use 'module_name instance_name();' to instantiate [OK]

Common Mistakes:

• Swapping instance and module names
• Using 'module' keyword during instantiation
• Adding extra keywords like 'inst'

3. Given the following top module code, what is the width of the output signal result?

module alu(input [3:0] a, input [3:0] b, output [4:0] sum);
  assign sum = a + b;
endmodule

module top();
  wire [4:0] result;
  wire [3:0] x = 4'b1010;
  wire [3:0] y = 4'b0101;
  alu alu_inst(.a(x), .b(y), .sum(result));
endmodule

medium

A. 4 bits

B. 5 bits

C. 3 bits

D. 8 bits

Solution

1. Step 1: Check the output width in the submodule

   The alu module defines sum as 5 bits wide: output [4:0] sum.

2. Step 2: Confirm connection in top module

   The top module connects result wire as 5 bits wide to sum.

3. Final Answer:

   5 bits -> Option B

4. Quick Check:

   Output width matches submodule definition = 5 bits [OK]

Hint: Output width matches submodule port width [OK]

Common Mistakes:

• Assuming output width equals input width
• Ignoring declared wire width in top module
• Confusing bit ranges like [4:0] as 4 bits

4. Identify the error in this top module integration code:

module adder(input [3:0] a, input [3:0] b, output [4:0] sum);
  assign sum = a + b;
endmodule

module top();
  wire [4:0] result;
  wire [3:0] x = 4'b0011;
  wire [3:0] y = 4'b0101;
  adder add_inst(.a(x), .b(y), .sum(sum));
endmodule

medium

A. Incorrect bit width for 'result'

B. Module 'adder' is missing ports

C. Signal 'sum' is not declared in top module

D. Instance name 'add_inst' is invalid

Solution

1. Step 1: Check port connections in top module

   The instance connects .sum(sum), but sum is not declared in top module.

2. Step 2: Verify declared signals

   Only result is declared as 5-bit wire, but not sum.

3. Final Answer:

   Signal 'sum' is not declared in top module -> Option C

4. Quick Check:

   Port connection must match declared signals [OK]

Hint: Check all connected signals are declared in top module [OK]

Common Mistakes:

• Using undeclared signals in port connections
• Assuming instance names affect correctness
• Ignoring port width mismatches

5. You want to integrate two modules, counter and display, in a top module. The counter outputs a 4-bit count signal, and display takes a 4-bit input to show the count. Which of the following top module code snippets correctly connects these modules?

hard

A. module top();
wire [3:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

B. module top();
wire count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

C. module top();
wire [4:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

D. module top();
reg [3:0] count;
counter c1(.count_out(count));
display d1(.data_in(count));
endmodule

Solution

1. Step 1: Match signal widths

   The counter outputs 4 bits, so count must be 4 bits wide wire.

2. Step 2: Use wire for inter-module connection

   Signals connecting modules should be wires, not regs, unless driven inside the module.

3. Step 3: Verify port names and connections

   module top(); wire [3:0] count; counter c1(.count_out(count)); display d1(.data_in(count)); endmodule correctly connects count_out to count and data_in to count.

4. Final Answer:

   module top(); wire [3:0] count; counter c1(.count_out(count)); display d1(.data_in(count)); endmodule -> Option A

5. Quick Check:

   Correct width and wire type for inter-module signals [OK]

Hint: Use wire with correct width to connect modules [OK]

Common Mistakes:

• Using reg instead of wire for connections
• Mismatching signal widths
• Declaring signals with wrong bit size